"Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation."

Fuqiang Li et al. (2016)

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DOI: 10.1587/TRANSFUN.E99.A.2310

access: closed

type: Journal Article

metadata version: 2020-04-11

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Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara:
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2310-2319 (2016)

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