A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
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Mar 22, 2025 - Verilog
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rtl-design
Here are 23 public repositories matching this topic...
The Repository contains the code of various Digital Circuits
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Aug 7, 2023 - Verilog
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
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Aug 4, 2024 - Verilog
probable journey of RTL coding ft. Chandra Prakash
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Mar 14, 2024 - Verilog
RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor
vhdl embedded-systems hardware-designs computer-architecture dlx digital-design risc-processor dlx-instruction-set rtl-design dlx-processor
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Dec 22, 2022 - Verilog
This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory, and comprehensive testbenches. Includes scripts for fast simulation and synthesis using QuestaSim, Vivado and Quartus Prime
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Sep 5, 2024 - Verilog
Scan insertion and design of a LBIST wrapper for a RISC-V core for stuck-at fault model
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Jan 17, 2022 - Verilog
This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book.
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Jan 1, 2025 - Verilog
RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
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Apr 7, 2024 - Verilog
an RTL circuit that sorts the integer values in a momory unit connected with (almost) AXI-Lite
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Jul 19, 2023 - Verilog
RTL Design of Inter-Integrated Circuit
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Jan 1, 2024 - Verilog
Digital Logical Designs Course Projects
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Aug 19, 2022 - Verilog
Advanced Pheripheral Bus design using verilog HDL
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Sep 7, 2021 - Verilog
RTL Design of Serial Peripheral Interface
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Dec 12, 2023 - Verilog
Integration of Arty A7-100T with MPU-6050 Gyroscope Sensor for Motion Sensing and FPGA Testing
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Jan 15, 2024 - Verilog
RTL Design of Universal Asynchronous Receiver-Transmitter
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Dec 3, 2023 - Verilog
This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.
circuit-simulation verilog-hdl test-bench half-adder hardware-description-language digital-electronics full-adder verilog-project vlsi-design rtl-design arithmetic-operations fpga-verilog logic-circuit-design behavioral-modeling 4-bit-adder verilog-adders gate-level-design dataflow-design digital-circuit-simulation hdl-coding
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Aug 24, 2024 - Verilog
An open-source Verilog implementation of UART featuring 8-bit and 32-bit architectures with simulation support for efficient data exchange.
verilog uart serial-communication data-transmission rtl-design testbench-verification serial-communication-protocol asynchronous-transmission
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Dec 19, 2023 - Verilog
RTL code of an 8-bit CPU designed in Verilog.
personal-project learning-by-doing computer-architecture verilog-hdl cpu-architecture rtl-design testbench-verification
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Aug 12, 2024 - Verilog
The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.
fpga algorithms rtl verilog fulladder algorithms-implemented multiplier halfadder fpga-programming asic-design rtl-design multipliers
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May 27, 2024 - Verilog
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