Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
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Mar 24, 2021 - Verilog
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risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 268 public repositories matching this topic...
RISC-V CPU Core (RV32IM)
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Sep 18, 2021 - Verilog
32-bit Superscalar RISC-V CPU
linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors
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Sep 18, 2021 - Verilog
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
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Dec 2, 2019 - Verilog
RISC-V Embedded Processor for Approximate Computing
cpu fpga embedded-systems riscv microprocessor computer-architecture vlsi risc-v approximate-computing cpu-design
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Apr 11, 2025 - Verilog
Basic RISC-V Test SoC
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Apr 7, 2019 - Verilog
Verilog implementation of multi-stage 32-bit RISC-V processor
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Nov 2, 2020 - Verilog
XCrypto: a cryptographic ISE for RISC-V
open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto
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Jan 5, 2023 - Verilog