Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

This project provides a TCL command for PrimeTime, enabling a straightforward implementation of a post-synthesis leakage power minimization procedure. Developed as part of a contest project for the course "Synthesis and Optimization of Digital Circuits" at Politecnico di Torino. This tool is designed to streamline power optimization efforts.