OpenGL 1.x implementation for FPGAs

This project implements a convolution kernel based on vivado HLS on zcu104

Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)

The codebase that computed the Ninth Dedekind Number

HLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA

EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.

A lightweight cloudFPGA prototype for processor simulation. It provides online scalable route resources with only open source synthesis toolset.

Predicting 3D human pose from single image using a VCK5000 Versal Development Card

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

A framework for Automated Design Space Exploration