asic

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

asic encryption fpga aes block-cipher

Updated Apr 3, 2025
Verilog

dpretet / async_fifo

Sponsor

Star

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Apr 30, 2024
Verilog

pulp-platform / cheshire

Star

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

asic fpga simulation riscv systemverilog rtl-design

Updated Apr 14, 2025
Verilog

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

Star

IC implementation of Systolic Array for TPU

asic fpga rtl verilog asic-verification asic-design

Updated Oct 21, 2024
Verilog

Juniper / open-register-design-tool

Star

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

asic fpga eda systemverilog uvm registers systemrdl jspec register-descriptions systemrdl-compiler

Updated Oct 21, 2024
Verilog

furrtek / SiliconRE

Star

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

asic fpga arcade-game video-game reverse-engineering arcade verilog chip konami hdl silicon cpld repro taito decap gate-array standard-cell

Updated Mar 26, 2025
Verilog

ulixxe / usb_cdc

Star

Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs

asic fpga serial usb verilog bootloader usb-cdc cdc-acm usb-device tinyfpga-bx fomu

Updated Mar 10, 2024
Verilog

KASIRGA-KIZIL / tekno-kizil

Star

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

asic cpu fpga processor llvm verification clang riscv rtl verilog computer-architecture pipeline-processor in-order risc-v coremark rv32imc teknofest openlane

Updated Jul 20, 2023
Verilog

thedatabusdotio / fpga-ml-accelerator

Star

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

asic fpga hardware vhdl verification verilog-hdl digital-design

Updated Jun 20, 2024
Verilog

rejunity / tiny-asic-1_58bit-matrix-mul

Star

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

asic systolic-arrays tinytapeout llm-inference

Updated Apr 19, 2024
Verilog

WilsonChen003 / HDLGen

Star

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

python automation asic script perl rtl verilog hdl soc