This project implements an AES (Advanced Encryption Standard) encryption and decryption core in Verilog. It supports multiple key lengths (128-bit, 192-bit, and 256-bit) and provides both encryption and decryption functionality.

• Supports AES-128, AES-192, and AES-256 key sizes
• Implements both encryption and decryption
• Modular design with clearly separated AES transformations
• **Configurable parameter **********enc_dec: (for ShiftRows and MixColumns module)
  • 0 for encryption
  • 1 for decryption
• Synthesizable and simulation-ready

Two main Modules AES_encrypt.v and AES_decrypt.v. The design is structured into several submodules, each responsible for a specific transformation in the AES process:

• KeyExpansion – Expands the input key to generate round keys
• AddRoundKey – XORs the data with the round key
• SubByte – Byte substitution using the SBox
• InvSubByte – Inverse byte substitution using InvSBox
• MixColumns – Implements both direct (encryption) and inverse (decryption) transformations, selected based on enc_dec
• ShiftRows – Implements both direct (encryption) and inverse (decryption) row shifting, selected based on enc_dec
• SBox – Substitution box for encryption
• InvSBox – Inverse substitution box for decryption

Encryption Module AES_encrypt.v implemented to match this Pseudo code in the standard

Cipher(byte in[4*Nb], byte out[4*Nb], word w[Nb*(Nr+1)]) 
begin 
	byte state[4,Nb] 
	state = in 
	AddRoundKey(state, w[0, Nb-1]) 
	for round = 1 step 1 to Nr–1 
		SubBytes(state) 
		ShiftRows(state) 
		MixColumns(state) 
		
		AddRoundKey(state, w[round*Nb, (round+1)*Nb-1]) 
	end for 
	SubBytes(state) 
	ShiftRows(state) 
	AddRoundKey(state, w[Nr*Nb, (Nr+1)*Nb-1]) 
	out = state 
end 

Decryption Module AES_decrypt.v implemented to match this Pseudo code in the standard

InvCipher(byte in[4*Nb], byte out[4*Nb], word w[Nb*(Nr+1)]) 
begin 
	byte state[4,Nb] 
	state = in 
	AddRoundKey(state, w[Nr*Nb, (Nr+1)*Nb-1])
	for round = Nr-1 step -1 downto 1 
		InvShiftRows(state) 
		InvSubBytes(state) 
		AddRoundKey(state, w[round*Nb, (round+1)*Nb-1]) 
		InvMixColumns(state)
	end for 
	
	InvShiftRows(state) 
	InvSubBytes(state) 
	AddRoundKey(state, w[0, Nb-1]) 
	out = state 
end 

The testbench integrate both Encryption and decryption modules. Multiple inputs (plain texts) where inserted with different keys and all passed, here are some snipps:

1. AES-128
2. AES-192
3. AES-256 to run the project you can use run.do

Abdelrahman Ahmed : MixColumns.v, AES_encrypt.v, AES_TB.v

Ahmed Kamel : KeyExpansion.v, AES_encrypt.v

Fatma Saad : SubByte.v & InvSubByte.v, AES_decrypt.v

Alaa Elshahawy : AddRoundKey, ShiftRows.v, AES_decrypt.v