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Ryzen 9 3950X
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CoreFreq version 1.92 |
Processor Information
Processor [AMD Ryzen 9 3950X 16-Core Processor]
|- Architecture [Zen2/Matisse]
|- Vendor ID [AuthenticAMD]
|- Firmware [ 46.72.0-2]
|- Microcode [0x08701021]
|- Signature [ 8F_71]
|- Stepping [ 0]
|- Online CPU [ 32/ 32]
|- Base Clock [ 99.981]
|- Frequency (MHz) Ratio
Min 2199.57 < 22 >
Max 3499.32 < 35 >
|- Factory [100.000]
3500 [ 35 ]
|- Performance
|- P-State
TGT 3499.32 < 35 >
|- CPPC
Min 499.90 < 5 >
Max 4699.09 < 47 >
TGT 4699.09 < 47 >
|- Turbo Boost [ UNLOCK]
XFR 4799.07 [ 48 ]
CPB 4699.09 [ 47 ]
1C 2799.46 < 28 >
2C 2199.57 < 22 >
|- Uncore [ LOCK]
CLK 1799.65 [ 18 ]
MEM 5498.94 [ 55 ]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [N] AVX-FP128 [N] AVX-FP256 [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [Y] UMIP [Y]
|- VAES [N] VPCLMULQDQ [N] PREFETCH/W [Y] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- Advanced Virtual Interrupt Controller AVIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Clear Zero Instruction CLZERO [Capable]
|- Core Multi-Processing CMP Legacy [Capable]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Collaborative Processor Performance Control CPPC [Capable]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast Short REP MOVSB FSRM [Missing]
|- Fast-String Operation ERMS [Missing]
|- Fused Multiply Add FMA | FMA4 [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hardware P-state control HwP [Capable]
|- Instruction Based Sampling IBS [Capable]
|- Instruction INVLPGB INVLPGB [Missing]
|- Instruction INVPCID INVPCID [Missing]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Memory Bandwidth Enforcement MBE [Capable]
|- Machine-Check Architecture MCA [Capable]
|- Instruction MCOMMIT MCOMMIT [Missing]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Capable]
|- Read Processor Register at User level RDPRU [Capable]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Missing]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Capable]
|- Extended xAPIC Support x2APIC [ xAPIC]
|- AVIC controller for x2APIC x2AVIC [Missing]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [ Unable]
|- IBRS Always-On preferred by processor [ Unable]
|- IBRS preferred over software solution [Capable]
|- IBRS provides same speculation limits [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- SSBD use VIRT_SPEC_CTRL register [ Unable]
|- SSBD not needed on this processor [ Unable]
|- No Branch Type Confusion BTC_NO [ Unable]
|- BTC on Non-Branch instruction BTC-NOBR [ Enable]
|- Arch - No Fast Predictive Store Forwarding PSFD [ Unable]
Security Features
|- Secure Init and Jump with Attestation SKINIT [Capable]
|- Secure Encrypted Virtualization SEV [Capable]
|- SEV - Encrypted State SEV-ES [Capable]
|- SEV - Secure Nested Paging SEV-SNP [Missing]
|- Guest Mode Execute Trap GMET [Capable]
|- Supervisor Shadow Stack SSS [Missing]
|- VM Permission Levels VMPL [Missing]
|- VMPL Supervisor Shadow Stack VMPL-SSS [Missing]
|- Secure Memory Encryption SME [Capable]
|- Transparent SME TSME [Disable]
|- Secure Multi-Key Memory Encryption SME-MK [Missing]
|- DRAM Data Scrambling Scrambler [ Enable]
Technologies
|- Instruction Cache Unit
|- L1 IP Prefetcher L1 HW IP < ON>
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- L2 Prefetcher L2 HW < ON>
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [ ON]
|- Core C-States CCx [ ON]
|- Core Performance Boost CPB < ON>
|- Watchdog Timer WDT < ON>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [ ON]
|- Version [ 0.1]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 1]
|- Counters: General Fixed
| { 6, 6, 4 } x 48 bits 3 x 64 bits
|- Enhanced Halt State C1E <OFF>
|- C2 UnDemotion C2U <OFF>
|- C3 UnDemotion C3U < ON>
|- Core C6 State CC6 < ON>
|- Package C6 State PC6 < ON>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Core C-States
|- C-States Base Address BAR [ 0x413 ]
|- ACPI Processor C-States _CST [ 2]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 1 1 0 0 0 0 0 0
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Global Time Stamp Counter [Missing]
|- Data Fabric Performance Counter [Capable]
|- Core Performance Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 3]
|- Performance Present Capabilities _PPC [ 0]
|- Continuous Performance Control _CPC [ Enable]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax [ 49: 95 C]
|- CPPC Energy Preference EPP [Missing]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TTP [ Enable]
|- Thermal Monitor 2 HTC [ Enable]
|- Thermal Design Power TDP [ 105 W]
|- Minimum Power Min [ 105 W]
|- Maximum Power Max [ 105 W]
|- Thermal Design Power Package < Enable>
|- Power Limit PL1 < 142 W>
|- Time Window TW1 < 0 ns>
|- Power Limit PL2 < 395 W>
|- Time Window TW2 < 0 ns>
|- Thermal Design Power Core [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Uncore [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power DRAM [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Platform [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 0 ns]
|- Package Power Tracking PPT [ 142 W]
|- Electrical Design Current EDC [ 140 A]
|- Thermal Design Current TDC [ 95 A]
|- Core Thermal Point
|- Package Thermal Point
|- Thermal Monitor Trip Limit [ 115 C]
|- HTC Temperature Limit Limit [ 127 C]
|- HTC Temperature Hysteresis Threshold [ 2 C]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000015259]
|- Window second [ 0.000976562]
CPPC
|- Collaborative Processor Performance Control CPPC <FMW>
|- Capabilities Lowest Efficient Guaranteed Highest
|- CPU #0 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4700.00 ( 47)
|- CPU #1 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4700.00 ( 47)
|- CPU #2 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4600.00 ( 46)
|- CPU #3 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4500.00 ( 45)
|- CPU #4 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4200.00 ( 42)
|- CPU #5 500.00 ( 5) 3499.99 ( 35) 2399.99 ( 24) 4399.99 ( 44)
|- CPU #6 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4100.00 ( 41)
|- CPU #7 500.00 ( 5) 3499.99 ( 35) 2399.99 ( 24) 4299.99 ( 43)
|- CPU #8 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 3800.00 ( 38)
|- CPU #9 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4000.00 ( 40)
|- CPU #10 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 3700.00 ( 37)
|- CPU #11 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 3900.00 ( 39)
|- CPU #12 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 3400.00 ( 34)
|- CPU #13 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 3600.00 ( 36)
|- CPU #14 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 3300.00 ( 33)
|- CPU #15 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 3500.00 ( 35)
|- CPU #16 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4700.00 ( 47)
|- CPU #17 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4700.00 ( 47)
|- CPU #18 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4600.00 ( 46)
|- CPU #19 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4500.00 ( 45)
|- CPU #20 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4200.00 ( 42)
|- CPU #21 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4400.00 ( 44)
|- CPU #22 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4100.00 ( 41)
|- CPU #23 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4300.00 ( 43)
|- CPU #24 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 3800.00 ( 38)
|- CPU #25 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 4000.00 ( 40)
|- CPU #26 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 3700.00 ( 37)
|- CPU #27 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 3900.00 ( 39)
|- CPU #28 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 3400.00 ( 34)
|- CPU #29 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 3600.00 ( 36)
|- CPU #30 500.00 ( 5) 3499.97 ( 35) 2399.98 ( 24) 3299.97 ( 33)
|- CPU #31 500.00 ( 5) 3500.00 ( 35) 2400.00 ( 24) 3500.00 ( 35)
System Information
ROG Crosshair VIII (WiFi)
BIOS 4201
[ 0] American Megatrends Inc.
[ 1] 4201
[ 2] 04/26/2022
[ 3] ASUS
[ 4] System Product Name
[ 5] System Version
[ 6] S---e---e---l---m---
[ 7] SKU
[ 8] To be filled by O.E.M.
[ 9] ASUSTeK COMPUTER INC.
[10] ROG CROSSHAIR VIII HERO (WI-FI)
[11] Rev X.0x
[12] 2---6---3---0--
[13] Number Of Devices:4\Maximum Capacity:134217728 kilobytes
[14]
[15] DIMM_A2\BANK 1
[16]
[17] DIMM_B2\BANK 3
[18]
[19] G Skill Intl
[20]
[21] G Skill Intl
[22]
[23] F4-3600C16-16GTZN
[24]
[25] F4-3600C16-16GTZN
Kernel
Linux:
|- Release [6.1.9-arch1-2]
|- Version [#1 SMP PREEMPT_DYNAMIC Fri, 03 Feb 2023 18:49:53 +0000]
|- Machine [x86_64]
Memory:
|- Total RAM 32778944 KB
|- Shared RAM 22728 KB
|- Free RAM 28387044 KB
|- Buffer RAM 103376 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < tsc>
CPU-Freq driver [ corefreqk-perf]
Governor [ corefreq-policy]
CPU-Idle driver [ corefreqk-idle]
|- Idle Limit < C2>
|- State POLL C1 C2 C3 C4 C5 C6
|- CPUIDLE I/O-C1 I/O-C2 I/O-C3 I/O-C4 I/O-C5 I/O-C6
|- Power -1 0 0 0 0 0 0
|- Latency 0 1 20 40 60 80 100
|- Residency 0 2 40 80 120 160 200
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Processor
Frequencies
IPC
TSC
Idle states
Vcore, Power & Thermal
Memory Controller
Optimized timings
Overclocking
Max Frequency P-State
Power Limit
PL1 @
142W
PL1 @
148W
Features
Technologies
Capabilities
ISA