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Created August 27, 2024 04:48
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Ryzen 9 9950X
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gistfile1.txt
AMD Ryzen 9 9950X 16-Core Processor
@cyring
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cyring commented Aug 27, 2024 •
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Processor                                  [AMD Ryzen 9 9950X 16-Core Processor]
|- Architecture                                             [Zen5/Granite Ridge]
|- Vendor ID                                                      [AuthenticAMD]
|- Microcode                                                        [0x0b40401a]
|- Signature                                                           [  BF_44]
|- Stepping                                                            [      0]
|- Online CPU                                                          [ 32/ 32]
|- Base Clock                                                          [ 99.983]
|- Frequency            (MHz)                      Ratio                        
                 Min   2999.50                    <  30 >                       
                 Max   4299.28                    <  43 >                       
|- Factory                                                             [100.000]
                       4300                       [  43 ]                       
|- Performance                                                                  
                 TGT   4299.28                    <  43 >                       
   |- CPPC                                                                      
                 Min   3699.38                    <  37 >                       
                 Max    399.93                    <   4 >                       
                 TGT      AUTO                    <   0 >                       
   |- Boost                                                            [ UNLOCK]
                 XFR   5699.05                    [  57 ]                       
                 CPB   5699.05                    [  57 ]                       
   |- P-State                                                                   
                 P1    2999.50                    <  30 >                       
|- Uncore                                                              [   LOCK]
                 CLK   1499.75                    [  15 ]                       
                 MEM   2999.50                    [  30 ]                       
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y] 
|- AVX512-F     [Y]    AVX512-DQ [Y]  AVX512-IFMA [Y]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [Y]    AVX512-BW [Y]   AVX512-VL [Y] 
|- AVX512-VBMI  [Y] AVX512-VBMI2 [Y]  AVX512-VNNI [Y]  AVX512-ALG [Y] 
|- AVX512-VPOP  [Y] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [Y] 
|- AVX512-BF16  [Y] AVX-VNNI-VEX [Y]    AVX-FP128 [N]   AVX-FP256 [N] 
|- BMI1/BMI2  [Y/Y]         CLWB [Y]      CLFLUSH [Y] CLFLUSH-OPT [Y] 
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- MMX/Ext    [Y/Y] MON/MWAITX [Y/Y]        MOVBE [Y]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y] 
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/Y]      SSE4.2 [Y] 
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [Y]        UMIP [Y] 
|- VAES         [Y]   VPCLMULQDQ [Y]   PREFETCH/W [Y]       LZCNT [Y] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- 100 MHz multiplier Control                            100MHzSteps   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- Advanced Virtual Interrupt Controller                        AVIC   [Missing]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- LOCK prefix to read CR8                                    AltMov   [Capable]
|- Clear Zero Instruction                                     CLZERO   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Capable]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Collaborative Processor Performance Control                  CPPC   [Capable]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Missing]
|- CPL Qualified Debug Store                                  DS-CPL   [Missing]
|- 64-Bit Debug Store                                         DTES64   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Capable]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                           FMA4   [Missing]
|- Fused Multiply Add                                            FMA   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Hyper-Threading Technology                                    HTT   [Capable]
|- Hardware P-state control                                      HwP   [Capable]
|- Instruction Based Sampling                                    IBS   [Capable]
|- Instruction INVLPGB                                       INVLPGB   [Missing]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Memory Bandwidth Enforcement                                  MBE   [Capable]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Instruction MCOMMIT                                       MCOMMIT   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- No-Execute Page Protection                                     NX   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- OS Visible Work-around                                       OSVW   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Missing]
|- Process Context Identifiers                                  PCID   [Missing]
|- Perfmon and Debug Capability                                 PDCM   [Missing]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Capable]
|- Resource Director Technology/PQM                            RDT-M   [Capable]
|- Read Processor Register at User level                       RDPRU   [Capable]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Missing]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Trailing Bit Manipulation                                     TBM   [Missing]
|- Translation Cache Extension                                   TCE   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Missing]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Missing]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Capable]
|- Extended xAPIC Support                                     x2APIC   [  xAPIC]
|- AVIC controller for x2APIC                                 x2AVIC   [Missing]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Missing]
|- Extended Operation Support                                    XOP   [Missing]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
   |- IBRS Always-On preferred by processor                            [ Unable]
   |- IBRS preferred over software solution                            [Capable]
   |- IBRS provides same speculation limits                            [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [ Enable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
   |- SSBD use VIRT_SPEC_CTRL register                                 [ Unable]
   |- SSBD not needed on this processor                                [ Unable]
|- No Branch Type Confusion                                   BTC_NO   [Capable]
|- BTC on Non-Branch instruction                            BTC-NOBR   [Capable]
|- Limited Early Redirect Window                            AGENPICK   [ Unable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [Capable]
|- Arch - Enhanced Predictive Store Forwarding                  EPSF   [Capable]
|- Arch - Cross Processor Information Leak                XPROC_LEAK   [ Unable]
Security Features                                                               
|- CET Shadow Stack features                                  CET-SS   [Capable]
|- Secure Init and Jump with Attestation                      SKINIT   [Capable]
|- Secure Encrypted Virtualization                               SEV   [Missing]
|- SEV - Encrypted State                                      SEV-ES   [Missing]
|- SEV - Secure Nested Paging                                SEV-SNP   [Missing]
|- Guest Mode Execute Trap                                      GMET   [Capable]
|- Supervisor Shadow Stack                                       SSS   [Capable]
|- VM Permission Levels                                         VMPL   [Missing]
|- VMPL Supervisor Shadow Stack                             VMPL-SSS   [Missing]
|- Secure Memory Encryption                                      SME   [Capable]
|- Transparent SME                                              TSME   [ Enable]
|- Secure Multi-Key Memory Encryption                         SME-MK   [Missing]
|- DRAM Data Scrambling                                    Scrambler   [ Enable]
                                                                                
Technologies                                                                    
|- Instruction Cache Unit                                                       
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   < ON>
|- Cache Prefetchers                                                            
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L1 Stride Prefetcher                                     L1 Stride   < ON>
   |- L1 Region Prefetcher                                     L1 Region   < ON>
   |- L1 Burst Prefetch Mode                                    L1 Burst   < ON>
   |- L2 Stream HW Prefetcher                                  L2 Stream   < ON>
   |- L2 Up/Down Prefetcher                                   L2 Up/Down   < ON>
|- System Management Mode                                       SMM-Lock   [ ON]
|- Simultaneous Multithreading                                       SMT   [ ON]
|- PowerNow!                                                         CnQ   [ ON]
|- Core C-States                                                     CCx   [ ON]
|- Core Performance Boost                                            CPB   < ON>
|- Watchdog Timer                                                    WDT   < ON>
|- Virtualization                                                    SVM   [ ON]
   |- I/O MMU                                                      AMD-V   [ ON]
   |- Version                                                     [         0.1]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [  2]
|- Counters:          General                   Fixed                           
|           {  6,  4, 16 } x 48 bits            3 x 64 bits                     
|- Enhanced Halt State                                           C1E       <OFF>
|- C2 UnDemotion                                                 C2U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
|- Core C6 State                                                 CC6       < ON>
|- Package C6 State                                              PC6       < ON>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x413 ]
|- ACPI Processor C-States                                      _CST   [      3]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     1     2     0     0     0     0     0     0              
   |- Monitor-Mwait Extensions                                   EMX   [Capable]
   |- Interrupt Break-Event                                      IBE   [Capable]
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Global Time Stamp Counter                                           [Missing]
|- Data Fabric Performance Counter                                     [Capable]
|- Core Performance Counter                                            [Capable]
|- Processor Performance Control                                _PCT   [ Enable]
|- Performance Supported States                                 _PSS   [      2]
|- Performance Present Capabilities                             _PPC   [      0]
|- Continuous Performance Control                               _CPC   [Missing]
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax [ 49: 95 C]
|- CPPC Energy Preference                                        EPP   <      0>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Monitor 1                                             TTP   [ Enable]
|- Thermal Monitor 2                                             HTC   [ Enable]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Package Power Tracking                                        PPT   [Missing]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
|- Package Thermal Point                                                        
   |- Thermal Monitor Trip                                     Limit   [  115 C]
   |- HTC Temperature Limit                                    Limit   [  127 C]
   |- HTC Temperature Hysteresis                           Threshold   [    2 C]
|- Units                                                                        
   |- Power                                               watt   [      Missing]
   |- Energy                                             joule   [  0.000015259]
   |- Window                                            second   [  0.000976562]

|- Collaborative Processor Performance Control                  CPPC       < ON>
   |- Capabilities     Lowest      Efficient     Guaranteed        Highest      
   |- CPU #0     399.93 (  4)  1899.68 ( 19)  2799.53 ( 28)  5199.13 ( 52)      
   |- CPU #1     399.94 (  4)  1899.70 ( 19)  2799.56 ( 28)  5299.17 ( 53)      
   |- CPU #2     399.94 (  4)  1899.70 ( 19)  2799.56 ( 28)  4899.24 ( 49)      
   |- CPU #3     399.93 (  4)  1899.68 ( 19)  2799.54 ( 28)  4799.20 ( 48)      
   |- CPU #4     399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  5299.12 ( 53)      
   |- CPU #5     399.94 (  4)  1899.70 ( 19)  2799.56 ( 28)  5099.20 ( 51)      
   |- CPU #6     399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4599.25 ( 46)      
   |- CPU #7     399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4699.23 ( 47)      
   |- CPU #8     399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3999.35 ( 40)      
   |- CPU #9     399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4499.26 ( 45)      
   |- CPU #10    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4199.32 ( 42)      
   |- CPU #11    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4399.28 ( 44)      
   |- CPU #12    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3899.36 ( 39)      
   |- CPU #13    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4299.30 ( 43)      
   |- CPU #14    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3799.38 ( 38)      
   |- CPU #15    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3699.40 ( 37)      
   |- CPU #16    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  5199.14 ( 52)      
   |- CPU #17    399.94 (  4)  1899.69 ( 19)  2799.55 ( 28)  5299.14 ( 53)      
   |- CPU #18    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4899.20 ( 49)      
   |- CPU #19    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4799.22 ( 48)      
   |- CPU #20    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  5299.13 ( 53)      
   |- CPU #21    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  5099.17 ( 51)      
   |- CPU #22    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4599.25 ( 46)      
   |- CPU #23    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4699.23 ( 47)      
   |- CPU #24    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3999.35 ( 40)      
   |- CPU #25    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4499.27 ( 45)      
   |- CPU #26    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4199.31 ( 42)      
   |- CPU #27    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4399.28 ( 44)      
   |- CPU #28    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3899.36 ( 39)      
   |- CPU #29    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  4299.30 ( 43)      
   |- CPU #30    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3799.38 ( 38)      
   |- CPU #31    399.93 (  4)  1899.69 ( 19)  2799.54 ( 28)  3699.40 ( 37)      

                              Zen UMC  [14E0]                              
Controller #0                                                Dual Channel  
 Bus Rate  3000 MHz       Bus Speed 3000 MHz           DDR5 Speed 6000 MT/s
                                                                           
 Cha   CL  RCDr RCDw  RP  RAS   RC  RRDs RRDl FAW  WTRs WTRl  WR  clRR clWW
  #0   32   39   39   39  102  146    8   15   32    8   30   90    8   23 
  #1   32   39   39   39  102  146    8   15   32    8   30   90    8   23 
      CWL  RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
  #0   30   23   21    8    1   10   10    1   11   11    0    0    0    0 
  #1   30   23   22    8    1   10   10    1   11   11    0    0    0    0 
      REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt  Ban  Page  CKE  CMD  GDM  ECC
  #0 11677  312  192  390   0    0    ON OFF  R0W0   0    0   1T    ON   0 
  #1 11677  312  192  390   0    0    ON OFF  R0W0   0    0   1T    ON   0 
      MRD:PDA   MOD:PDA  WRMPR STAG PDM RDDATA WRD  WRL  RDL  XS   XP CPDED
  #0   42  32    42  32    24    7 0:F:1   20   6   18   36  914   23   15 
  #1   42  32    42  32    24    7 0:F:1   20   6   18   36  914   23   15 
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1    32    1     65536      1024          16384    F5-6400J3239G32G
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1    32    1     65536      1024          16384    F5-6400J3239G32G
  • Issue in DIMM geometry

@cyring
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cyring commented Sep 4, 2024 •
edited
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PRIME X670-P

image

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cyring commented Sep 4, 2024 •
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ROG STRIX X670E-E

1000002383

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cyring commented Nov 17, 2024

MPG X670E CARBON WIFI

Processor                                  [AMD Ryzen 9 9950X 16-Core Processor]
|- Architecture                                             [Zen5/Granite Ridge]
|- Vendor ID                                                      [AuthenticAMD]
|- Microcode                                                        [0x0b404022]
|- Signature                                                           [  BF_44]
|- Stepping                                                            [      0]
|- Online CPU                                                          [ 32/ 32]
|- Base Clock                                                          [ 99.813]
|- Frequency            (MHz)                      Ratio                        
                 Min   2994.39                    <  30 >                       
                 Max   4291.96                    <  43 >                       
|- Factory                                                             [100.000]
                       4300                       [  43 ]                       
|- Performance                                                                  
                 TGT   4291.96                    <  43 >                       
   |- CPPC                                                                      
                 Min   3693.08                    <  37 >                       
                 Max    399.25                    <   4 >                       
                 TGT      AUTO                    <   0 >                       
   |- Boost                                                            [ UNLOCK]
                 XFR   5689.34                    [  57 ]                       
                 CPB   5689.34                    [  57 ]                       
   |- P-State                                                                   
                 P1    2994.39                    <  30 >                       
|- Uncore                                                              [   LOCK]
                 CLK   1497.19                    [  15 ]                       
                 MEM   2994.39                    [  30 ]                       
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y] 
|- AVX512-F     [Y]    AVX512-DQ [Y]  AVX512-IFMA [Y]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [Y]    AVX512-BW [Y]   AVX512-VL [Y] 
|- AVX512-VBMI  [Y] AVX512-VBMI2 [Y]  AVX512-VNNI [Y]  AVX512-ALG [Y] 
|- AVX512-VPOP  [Y] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [Y] 
|- AVX512-BF16  [Y] AVX-VNNI-VEX [Y]    AVX-FP128 [N]   AVX-FP256 [N] 
|- BMI1/BMI2  [Y/Y]         CLWB [Y]      CLFLUSH [Y] CLFLUSH-OPT [Y] 
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- MMX/Ext    [Y/Y] MON/MWAITX [Y/Y]        MOVBE [Y]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y] 
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/Y]      SSE4.2 [Y] 
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [Y]        UMIP [Y] 
|- VAES         [Y]   VPCLMULQDQ [Y]   PREFETCH/W [Y]       LZCNT [Y] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- 100 MHz multiplier Control                            100MHzSteps   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- Advanced Virtual Interrupt Controller                        AVIC   [Missing]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- LOCK prefix to read CR8                                    AltMov   [Capable]
|- Clear Zero Instruction                                     CLZERO   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Capable]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Collaborative Processor Performance Control                  CPPC   [Capable]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Missing]
|- CPL Qualified Debug Store                                  DS-CPL   [Missing]
|- 64-Bit Debug Store                                         DTES64   [Missing]
|- Fast Short REP CMPSB|SCASB                                   FSRC   [Capable]
|- Fast Short REP MOVSB                                         FSRM   [Capable]
|- Fast Short REP STOSB                                         FSRS   [Capable]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                           FMA4   [Missing]
|- Fused Multiply Add                                            FMA   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Hyper-Threading Technology                                    HTT   [Capable]
|- Hardware P-state control                                      HwP   [Capable]
|- Instruction Based Sampling                                    IBS   [Capable]
|- Instruction INVLPGB                                       INVLPGB   [Missing]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Memory Bandwidth Enforcement                                  MBE   [Capable]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Instruction MCOMMIT                                       MCOMMIT   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- No-Execute Page Protection                                     NX   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- OS Visible Work-around                                       OSVW   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Missing]
|- Process Context Identifiers                                  PCID   [Missing]
|- Perfmon and Debug Capability                                 PDCM   [Missing]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- PREFETCHIT0/1 Instructions                              PREFETCHI   [Capable]
|- Resource Director Technology/PQE                            RDT-A   [Capable]
|- Resource Director Technology/PQM                            RDT-M   [Capable]
|- Read Processor Register at User level                       RDPRU   [Capable]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Missing]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Trailing Bit Manipulation                                     TBM   [Missing]
|- Translation Cache Extension                                   TCE   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Missing]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Missing]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Capable]
|- Extended xAPIC Support                                     x2APIC   [  xAPIC]
|- AVIC controller for x2APIC                                 x2AVIC   [Missing]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Missing]
|- Extended Operation Support                                    XOP   [Missing]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
   |- IBRS Always-On preferred by processor                            [ Unable]
   |- IBRS preferred over software solution                            [Capable]
   |- IBRS provides same speculation limits                            [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Selective Branch Predictor Barrier                           SBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [ Enable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
   |- SSBD use VIRT_SPEC_CTRL register                                 [ Unable]
   |- SSBD not needed on this processor                                [ Unable]
|- No Speculative Return Stack Overflow                      SRSO_NO   [ Unable]
   |- No SRSO at the User-Kernel boundary                              [Capable]
|- No Branch Type Confusion                                   BTC_NO   [Capable]
|- BTC on Non-Branch instruction                            BTC-NOBR   [Capable]
|- Limited Early Redirect Window                            AGENPICK   [ Unable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [Capable]
|- Arch - Enhanced Predictive Store Forwarding                  EPSF   [Capable]
|- Arch - Cross Processor Information Leak                XPROC_LEAK   [ Unable]
Security Features                                                               
|- CET Shadow Stack features                                  CET-SS   [Capable]
|- Secure Init and Jump with Attestation                      SKINIT   [Capable]
|- Secure Encrypted Virtualization                               SEV   [Missing]
|- SEV - Encrypted State                                      SEV-ES   [Missing]
|- SEV - Secure Nested Paging                                SEV-SNP   [Missing]
|- Guest Mode Execute Trap                                      GMET   [Capable]
|- Supervisor Shadow Stack                                       SSS   [Capable]
|- VM Permission Levels                                         VMPL   [Missing]
|- VMPL Supervisor Shadow Stack                             VMPL-SSS   [Missing]
|- Secure Memory Encryption                                      SME   [Capable]
|- Transparent SME                                              TSME   [ Enable]
|- Secure Multi-Key Memory Encryption                         SME-MK   [Missing]
|- DRAM Data Scrambling                                    Scrambler   [ Enable]
                                                                                
Technologies                                                                    
|- Instruction Cache Unit                                                       
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   < ON>
|- Cache Prefetchers                                                            
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L1 Stride Prefetcher                                     L1 Stride   < ON>
   |- L1 Region Prefetcher                                     L1 Region   < ON>
   |- L1 Burst Prefetch Mode                                    L1 Burst   < ON>
   |- L2 Stream HW Prefetcher                                  L2 Stream   < ON>
   |- L2 Up/Down Prefetcher                                   L2 Up/Down   < ON>
|- System Management Mode                                       SMM-Lock   [ ON]
|- Simultaneous Multithreading                                       SMT   [ ON]
|- PowerNow!                                                         CnQ   [ ON]
|- Core C-States                                                     CCx   [ ON]
|- Core Performance Boost                                            CPB   < ON>
|- Watchdog Timer                                                    WDT   < ON>
|- Virtualization                                                    SVM   [ ON]
   |- I/O MMU                                                      AMD-V   [ ON]
   |- Version                                                     [         0.1]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [  2]
|- Counters:          General                   Fixed                           
|           {  6,  6, 16 } x 48 bits            3 x 64 bits                     
|- Enhanced Halt State                                           C1E       <OFF>
|- C2 UnDemotion                                                 C2U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
|- Core C6 State                                                 CC6       < ON>
|- Package C6 State                                              PC6       < ON>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x413 ]
|- ACPI Processor C-States                                      _CST   [      3]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     1     2     0     0     0     0     0     0              
   |- Monitor-Mwait Extensions                                   EMX   [Capable]
   |- Interrupt Break-Event                                      IBE   [Capable]
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Global Time Stamp Counter                                           [Missing]
|- Data Fabric Performance Counter                                     [Capable]
|- Core Performance Counter                                            [Capable]
|- Processor Performance Control                                _PCT   [ Enable]
|- Performance Supported States                                 _PSS   [      2]
|- Performance Present Capabilities                             _PPC   [      0]
|- Continuous Performance Control                               _CPC   [Missing]
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax [ 49: 95 C]
|- CPPC Energy Preference                                        EPP   <      0>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Monitor 1                                             TTP   [ Enable]
|- Thermal Monitor 2                                             HTC   [ Enable]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Package Power Tracking                                        PPT   [Missing]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
|- Package Thermal Point                                                        
   |- Thermal Monitor Trip                                     Limit   [  115 C]
   |- HTC Temperature Limit                                    Limit   [  127 C]
   |- HTC Temperature Hysteresis                           Threshold   [    2 C]
|- Units                                                                        
   |- Power                                               watt   [      Missing]
   |- Energy                                             joule   [  0.000015259]
   |- Window                                            second   [  0.000976562]

|- Collaborative Processor Performance Control                  CPPC       < ON>
   |- Capabilities     Lowest      Efficient     Guaranteed        Highest      
   |- CPU #0     399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  5290.06 ( 53)      
   |- CPU #1     399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  5090.44 ( 51)      
   |- CPU #2     399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  4890.82 ( 49)      
   |- CPU #3     399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  5190.25 ( 52)      
   |- CPU #4     399.25 (  4)  1896.45 ( 19)  2794.76 ( 28)  5290.09 ( 53)      
   |- CPU #5     399.25 (  4)  1896.45 ( 19)  2794.77 ( 28)  4791.03 ( 48)      
   |- CPU #6     399.25 (  4)  1896.42 ( 19)  2794.73 ( 28)  4591.34 ( 46)      
   |- CPU #7     399.25 (  4)  1896.45 ( 19)  2794.76 ( 28)  4691.21 ( 47)      
   |- CPU #8     399.25 (  4)  1896.42 ( 19)  2794.72 ( 28)  4192.09 ( 42)      
   |- CPU #9     399.25 (  4)  1896.44 ( 19)  2794.76 ( 28)  4491.57 ( 45)      
   |- CPU #10    399.25 (  4)  1896.44 ( 19)  2794.76 ( 28)  3992.51 ( 40)      
   |- CPU #11    399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  3892.69 ( 39)      
   |- CPU #12    399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  4391.74 ( 44)      
   |- CPU #13    399.25 (  4)  1896.44 ( 19)  2794.76 ( 28)  4291.95 ( 43)      
   |- CPU #14    399.25 (  4)  1896.44 ( 19)  2794.76 ( 28)  3792.89 ( 38)      
   |- CPU #15    399.25 (  4)  1896.45 ( 19)  2794.77 ( 28)  3693.08 ( 37)      
   |- CPU #16    399.25 (  4)  1896.44 ( 19)  2794.76 ( 28)  5290.08 ( 53)      
   |- CPU #17    399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  5090.43 ( 51)      
   |- CPU #18    399.25 (  4)  1896.44 ( 19)  2794.76 ( 28)  4890.83 ( 49)      
   |- CPU #19    399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  5190.25 ( 52)      
   |- CPU #20    399.25 (  4)  1896.44 ( 19)  2794.76 ( 28)  5290.08 ( 53)      
   |- CPU #21    399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  4791.00 ( 48)      
   |- CPU #22    399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  4591.38 ( 46)      
   |- CPU #23    399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  4691.20 ( 47)      
   |- CPU #24    399.25 (  4)  1896.43 ( 19)  2794.74 ( 28)  4192.12 ( 42)      
   |- CPU #25    399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  4491.56 ( 45)      
   |- CPU #26    399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  3992.50 ( 40)      
   |- CPU #27    399.25 (  4)  1896.43 ( 19)  2794.74 ( 28)  3892.68 ( 39)      
   |- CPU #28    399.25 (  4)  1896.44 ( 19)  2794.76 ( 28)  4391.76 ( 44)      
   |- CPU #29    399.25 (  4)  1896.46 ( 19)  2794.78 ( 28)  4291.98 ( 43)      
   |- CPU #30    399.25 (  4)  1896.44 ( 19)  2794.75 ( 28)  3792.88 ( 38)      
   |- CPU #31    399.25 (  4)  1896.43 ( 19)  2794.74 ( 28)  3693.06 ( 37)      

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID CCD CCX ID/ID L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP    0   0  0   0  0      32  8        48 12      1024 16 i   65536 16w 
001:  0    2   0  0   1  0      32  8        48 12      1024 16 i   65536 16w 
002:  0    4   0  0   2  0      32  8        48 12      1024 16 i   65536 16w 
003:  0    6   0  0   3  0      32  8        48 12      1024 16 i   65536 16w 
004:  0    8   0  1   4  0      32  8        48 12      1024 16 i   65536 16w 
005:  0   10   0  1   5  0      32  8        48 12      1024 16 i   65536 16w 
006:  0   12   0  1   6  0      32  8        48 12      1024 16 i   65536 16w 
007:  0   14   0  1   7  0      32  8        48 12      1024 16 i   65536 16w 
008:  0   16   1  2   8  0      32  8        48 12      1024 16 i   65536 16w 
009:  0   18   1  2   9  0      32  8        48 12      1024 16 i   65536 16w 
010:  0   20   1  2  10  0      32  8        48 12      1024 16 i   65536 16w 
011:  0   22   1  2  11  0      32  8        48 12      1024 16 i   65536 16w 
012:  0   24   1  3  12  0      32  8        48 12      1024 16 i   65536 16w 
013:  0   26   1  3  13  0      32  8        48 12      1024 16 i   65536 16w 
014:  0   28   1  3  14  0      32  8        48 12      1024 16 i   65536 16w 
015:  0   30   1  3  15  0      32  8        48 12      1024 16 i   65536 16w 
016:  0    1   0  0   0  1      32  8        48 12      1024 16 i   65536 16w 
017:  0    3   0  0   1  1      32  8        48 12      1024 16 i   65536 16w 
018:  0    5   0  0   2  1      32  8        48 12      1024 16 i   65536 16w 
019:  0    7   0  0   3  1      32  8        48 12      1024 16 i   65536 16w 
020:  0    9   0  1   4  1      32  8        48 12      1024 16 i   65536 16w 
021:  0   11   0  1   5  1      32  8        48 12      1024 16 i   65536 16w 
022:  0   13   0  1   6  1      32  8        48 12      1024 16 i   65536 16w 
023:  0   15   0  1   7  1      32  8        48 12      1024 16 i   65536 16w 
024:  0   17   1  2   8  1      32  8        48 12      1024 16 i   65536 16w 
025:  0   19   1  2   9  1      32  8        48 12      1024 16 i   65536 16w 
026:  0   21   1  2  10  1      32  8        48 12      1024 16 i   65536 16w 
027:  0   23   1  2  11  1      32  8        48 12      1024 16 i   65536 16w 
028:  0   25   1  3  12  1      32  8        48 12      1024 16 i   65536 16w 
029:  0   27   1  3  13  1      32  8        48 12      1024 16 i   65536 16w 
030:  0   29   1  3  14  1      32  8        48 12      1024 16 i   65536 16w 
031:  0   31   1  3  15  1      32  8        48 12      1024 16 i   65536 16w 

Linux:                                                                          
|- Release                                                      [6.11.8-arch1-2]
|- Version              [#1 SMP PREEMPT_DYNAMIC Fri, 15 Nov 2024 15:35:07 +0000]
|- Machine                                                              [x86_64]
Memory:                                                                         
|- Total RAM                                                         96391868 KB
|- Shared RAM                                                          479268 KB
|- Free RAM                                                          88059840 KB
|- Buffer RAM                                                          181404 KB
|- Total High                                                               0 KB
|- Free High                                                                0 KB
Clock Source                                                  <             tsc>
CPU-Freq driver                                               [  amd-pstate-epp]
Governor                                                      [         Missing]
CPU-Idle driver                                               [       acpi_idle]
|- Idle Limit                                                 [              C3]
   |- State        POLL      C1      C2      C3                                 
   |-           CPUIDLE ACPI FF ACPI IO ACPI IO                                 
   |- Power          -1       0       0       0                                 
   |- Latency         0       1      18     350                                 
   |- Residency       0       2      36     700                                 


[ 0] American Megatrends International, LLC.                                    
[ 1] 1.L0                                                                       
[ 2] 10/16/2024                                                                 
[ 3] Micro-Star International Co., Ltd.                                         
[ 4] MS-7D70                                                                    
[ 5] 1.0                                                                        
[ 6] T---e---l--- ---O---M-                                                     
[ 7] To be filled by O.E.M.                                                     
[ 8] To be filled by O.E.M.                                                     
[ 9] Micro-Star International Co., Ltd.                                         
[10] MPG X670E CARBON WIFI (MS-7D70)                                            
[11] 1.0                                                                        
[12] 0---0---O---3---0-                                                         
[13] Number Of Devices:4\Maximum Capacity:134217728 kilobytes                   
[14]                                                                            
[15] DIMMA2\P0 CHANNEL A                                                        
[16]                                                                            
[17] DIMMB2\P0 CHANNEL B                                                        
[18]                                                                            
[19] Unknown                                                                    
[20]                                                                            
[21] Unknown                                                                    
[22]                                                                            
[23]                                                                            
[24]                                                                            
[25]                                                                            

                              Zen UMC  [14E0]                              
Controller #0                                                Dual Channel  
 Bus Rate  3000 MHz       Bus Speed 2994 MHz           DDR5 Speed 5988 MT/s
                                                                           
 Cha   CL  RCDr RCDw  RP  RAS   RC  RRDs RRDl FAW  WTRs WTRl  WR  clRR clWW
  #0   30   36   36   36   76  115    8   15   32    8   30   90    8   23 
  #1   30   36   36   36   76  115    8   15   32    8   30   90    8   23 
      CWL  RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
  #0   28   23   20    8    1   10   10    1   11   11    0    0    0    0 
  #1   28   23   21    8    1   10   10    1   11   11    0    0    0    0 
      REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt  Ban  Page  CKE  CMD  GDM  ECC
  #0 11677  312  192  390   0    0    ON OFF  R0W0   0    0   1T    ON   0 
  #1 11677  312  192  390   0    0    ON OFF  R0W0   0    0   1T    ON   0 
      MRD:PDA   MOD:PDA  WRMPR STAG PDM RDDATA WRD  WRL  RDL  XS   XP CPDED
  #0   42  32    42  32    24    7 0:F:0   18   6   16   36  914   23   15 
  #1   42  32    42  32    24    7 0:F:0   18   6   16   36  914   23   15 
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1    32    1    131072      1024          32768                    
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1    32    1    131072      1024          32768                    

CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000   34.90   210  1.3125   30  000000000000007971    0.121627808   0.121627808
001   26.58   210  1.3125   30  000000000000004161    0.063491821   0.063491821
002    8.17   210  1.3125   30  000000000000003017    0.046035767   0.046035767
003   23.45   210  1.3125   30  000000000000002965    0.045242310   0.045242310
004   37.92   223  1.3938   30  000000000000013871    0.211654663   0.211654663
005   13.94   210  1.3125   30  000000000000004211    0.064254761   0.064254761
006   20.67   210  1.3125   30  000000000000018689    0.285171509   0.285171509
007   28.04   210  1.3125   30  000000000000005459    0.083297729   0.083297729
008   47.41   210  1.3125   30  000000000000012823    0.195663452   0.195663452
009   44.70   210  1.3125   30  000000000000009486    0.144744873   0.144744873
010   46.94   210  1.3125   30  000000000000013664    0.208496094   0.208496094
011   32.25   223  1.3938   30  000000000000003899    0.059494019   0.059494019
012   43.66   223  1.3938   30  000000000000011133    0.169876099   0.169876099
013   25.41   223  1.3938   30  000000000000007207    0.109970093   0.109970093
014    9.41   223  1.3938   30  000000000000003579    0.054611206   0.054611206
015   20.55   223  1.3938   30  000000000000001690    0.025787354   0.025787354
016   24.12   210  1.3125   30  000000000000000000    0.000000000   0.000000000
017    8.76   210  1.3125   30  000000000000000000    0.000000000   0.000000000
018    5.79   223  1.3938   30  000000000000000000    0.000000000   0.000000000
019    0.91   223  1.3938   30  000000000000000000    0.000000000   0.000000000
020   30.66   223  1.3938   30  000000000000000000    0.000000000   0.000000000
021    1.99   223  1.3938   30  000000000000000000    0.000000000   0.000000000
022    9.36   223  1.3938   30  000000000000000000    0.000000000   0.000000000
023    4.33   223  1.3938   30  000000000000000000    0.000000000   0.000000000
024    0.76   223  1.3938   30  000000000000000000    0.000000000   0.000000000
025   19.48   223  1.3938   30  000000000000000000    0.000000000   0.000000000
026   15.80   223  1.3938   30  000000000000000000    0.000000000   0.000000000
027    0.46   223  1.3938   30  000000000000000000    0.000000000   0.000000000
028   32.63   223  1.3938   30  000000000000000000    0.000000000   0.000000000
029   15.96   223  1.3938   30  000000000000000000    0.000000000   0.000000000
030   11.04   223  1.3938   30  000000000000000000    0.000000000   0.000000000
031    2.10   223  1.3938   30  000000000000000000    0.000000000   0.000000000

             Package[0]    Cores         Uncore        Memory        Platform
Energy(J):  36.569503784   1.889419556   0.000000000   0.000000000   0.000000000
Power(W) :  36.569503784   1.889419556   0.000000000   0.000000000   0.000000000


CPU Freq(MHz) Ratio  Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)  Min TMP:TS  Max
000   28.23 ( 0.28)   0.66   0.74  99.26   0.00   0.00   0.00  29 / 29:631/ 33
001   20.74 ( 0.21)   0.48   0.59  99.41   0.00   0.00   0.00  29 / 29:631/ 33
002   11.09 ( 0.11)   0.26   0.32  99.68   0.00   0.00   0.00  29 / 29:631/ 33
003   36.47 ( 0.37)   0.85   1.01  98.99   0.00   0.00   0.00  29 / 29:631/ 33
004   38.70 ( 0.39)   0.90   1.10  98.90   0.00   0.00   0.00  29 / 29:631/ 32
005   12.08 ( 0.12)   0.28   0.34  99.66   0.00   0.00   0.00  29 / 29:631/ 32
006   17.36 ( 0.17)   0.40   0.46  99.54   0.00   0.00   0.00  29 / 29:631/ 33
007    9.20 ( 0.09)   0.21   0.26  99.74   0.00   0.00   0.00  29 / 29:631/ 33
008   24.76 ( 0.25)   0.58   0.72  99.28   0.00   0.00   0.00  28 / 30:632/ 32
009   54.30 ( 0.54)   1.27   1.52  98.48   0.00   0.00   0.00  28 / 30:632/ 32
010   37.85 ( 0.38)   0.88   1.04  98.96   0.00   0.00   0.00  28 / 30:632/ 32
011   31.71 ( 0.32)   0.74   0.94  99.06   0.00   0.00   0.00  28 / 30:632/ 32
012   52.19 ( 0.52)   1.22   1.38  98.62   0.00   0.00   0.00  28 / 30:632/ 32
013   15.81 ( 0.16)   0.37   0.49  99.51   0.00   0.00   0.00  28 / 30:632/ 32
014    1.63 ( 0.02)   0.04   0.05  99.95   0.00   0.00   0.00  28 / 30:632/ 32
015   46.79 ( 0.47)   1.09   1.30  98.70   0.00   0.00   0.00  28 / 30:632/ 32
016   43.05 ( 0.43)   1.00   1.13  98.87   0.00   0.00   0.00  29 / 29:631/ 32
017   16.77 ( 0.17)   0.39   0.50  99.50   0.00   0.00   0.00  29 / 29:631/ 32
018   12.79 ( 0.13)   0.30   0.36  99.64   0.00   0.00   0.00  29 / 29:631/ 32
019    0.79 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  29 / 29:631/ 32
020    3.76 ( 0.04)   0.09   0.11  99.89   0.00   0.00   0.00  29 / 29:631/ 32
021   12.60 ( 0.13)   0.29   0.36  99.64   0.00   0.00   0.00  29 / 29:631/ 32
022    0.94 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  29 / 29:631/ 32
023    5.74 ( 0.06)   0.13   0.16  99.84   0.00   0.00   0.00  29 / 29:631/ 32
024    1.66 ( 0.02)   0.04   0.05  99.96   0.00   0.00   0.00  28 / 30:632/ 32
025   22.13 ( 0.22)   0.52   0.63  99.37   0.00   0.00   0.00  28 / 30:632/ 32
026   17.22 ( 0.17)   0.40   0.48  99.52   0.00   0.00   0.00  28 / 30:632/ 32
027    0.56 ( 0.01)   0.01   0.02  99.98   0.00   0.00   0.00  28 / 30:632/ 32
028   33.81 ( 0.34)   0.79   0.91  99.09   0.00   0.00   0.00  28 / 30:632/ 32
029    6.20 ( 0.06)   0.14   0.18  99.82   0.00   0.00   0.00  28 / 30:632/ 32
030   10.44 ( 0.10)   0.24   0.32  99.68   0.00   0.00   0.00  28 / 30:632/ 32
031    0.50 ( 0.00)   0.01   0.01  99.99   0.00   0.00   0.00  28 / 30:632/ 32

    Averages:        Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)    TjMax:    Pkg:
                      0.46   0.55  99.45   0.00   0.00   0.00      95 C    30 C


CPU     IPS            IPC            CPI
000     0.002605/s     0.291306/c     3.432816/i
001     0.003048/s     0.343524/c     2.911003/i
002     0.001723/s     0.354651/c     2.819676/i
003     0.001392/s     0.228778/c     4.371056/i
004     0.003136/s     0.439292/c     2.276393/i
005     0.000428/s     0.252445/c     3.961252/i
006     0.000281/s     0.130945/c     7.636815/i
007     0.000039/s     0.163746/c     6.107037/i
008     0.001120/s     0.262768/c     3.805637/i
009     0.006669/s     0.407925/c     2.451431/i
010     0.002728/s     0.260002/c     3.846129/i
011     0.001386/s     0.234501/c     4.264376/i
012     0.004082/s     0.325046/c     3.076489/i
013     0.000606/s     0.251566/c     3.975104/i
014     0.000142/s     0.321934/c     3.106229/i
015     0.005347/s     0.592131/c     1.688817/i
016     0.004580/s     0.412166/c     2.426208/i
017     0.000074/s     0.230261/c     4.342893/i
018     0.000323/s     0.194825/c     5.132813/i
019     0.000039/s     0.153130/c     6.530415/i
020     0.000298/s     0.371056/c     2.695010/i
021     0.001774/s     0.360666/c     2.772646/i
022     0.000433/s     0.368849/c     2.711137/i
023     0.000248/s     0.160381/c     6.235152/i
024     0.000477/s     0.257580/c     3.882292/i
025     0.023563/s     2.599079/c     0.384752/i
026     0.002137/s     0.347687/c     2.876153/i
027     0.000057/s     0.219168/c     4.562703/i
028     0.002356/s     0.270080/c     3.702610/i
029     0.001007/s     0.185031/c     5.404488/i
030     0.000039/s     0.167513/c     5.969679/i
031     0.000037/s     0.180774/c     5.531764/i


CPU FLAG CF  ZF  SF  TF  IF  DF  OF IOPL NT  RF  VM  AC  VIF VIP ID 
#0        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#1        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#2        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#3        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#4        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#5        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#6        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#7        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#8        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#9        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#10       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#11       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#12       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#13       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#14       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#15       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#16       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#17       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#18       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#19       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#20       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#21       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#22       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#23       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#24       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#25       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#26       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#27       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#28       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#29       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#30       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
#31       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0 
CR0: PE  MP  EM  TS  ET  NE  WP  AM  NW  CD  PG CR3: PWT PCD U57 U48
#0    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#1    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#2    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#3    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#4    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#5    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#6    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#7    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#8    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#9    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#10   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#11   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#12   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#13   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#14   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#15   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#16   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#17   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#18   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#19   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#20   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#21   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#22   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#23   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#24   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#25   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#26   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#27   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#28   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#29   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#30   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
#31   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0 
CR4: VME PVI TSD DE  PSE PAE MCE PGE PCE FX XMM UMIP 5LP VMX SMX FS 
#0    0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#1    0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#2    0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#3    0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#4    0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#5    0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#6    0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#7    0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#8    0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#9    0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#10   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#11   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#12   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#13   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#14   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#15   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#16   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#17   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#18   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#19   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#20   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#21   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#22   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#23   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#24   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#25   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#26   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#27   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#28   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#29   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#30   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
#31   0   0   0   0   1   1   1   1   0   1   1   1   0   0   0   1 
CR4:PCID SAV  KL SME SMA PKE CET PKS U-I LAM FRD            CR8: TPL
#0    0   1   0   1   1   1   1   0   0   0   0                   0 
#1    0   1   0   1   1   1   1   0   0   0   0                   0 
#2    0   1   0   1   1   1   1   0   0   0   0                   0 
#3    0   1   0   1   1   1   1   0   0   0   0                   0 
#4    0   1   0   1   1   1   1   0   0   0   0                   0 
#5    0   1   0   1   1   1   1   0   0   0   0                   0 
#6    0   1   0   1   1   1   1   0   0   0   0                   0 
#7    0   1   0   1   1   1   1   0   0   0   0                   0 
#8    0   1   0   1   1   1   1   0   0   0   0                   0 
#9    0   1   0   1   1   1   1   0   0   0   0                   0 
#10   0   1   0   1   1   1   1   0   0   0   0                   0 
#11   0   1   0   1   1   1   1   0   0   0   0                   0 
#12   0   1   0   1   1   1   1   0   0   0   0                   0 
#13   0   1   0   1   1   1   1   0   0   0   0                   0 
#14   0   1   0   1   1   1   1   0   0   0   0                   0 
#15   0   1   0   1   1   1   1   0   0   0   0                   0 
#16   0   1   0   1   1   1   1   0   0   0   0                   0 
#17   0   1   0   1   1   1   1   0   0   0   0                   0 
#18   0   1   0   1   1   1   1   0   0   0   0                   0 
#19   0   1   0   1   1   1   1   0   0   0   0                   0 
#20   0   1   0   1   1   1   1   0   0   0   0                   0 
#21   0   1   0   1   1   1   1   0   0   0   0                   0 
#22   0   1   0   1   1   1   1   0   0   0   0                   0 
#23   0   1   0   1   1   1   1   0   0   0   0                   0 
#24   0   1   0   1   1   1   1   0   0   0   0                   0 
#25   0   1   0   1   1   1   1   0   0   0   0                   0 
#26   0   1   0   1   1   1   1   0   0   0   0                   0 
#27   0   1   0   1   1   1   1   0   0   0   0                   0 
#28   0   1   0   1   1   1   1   0   0   0   0                   0 
#29   0   1   0   1   1   1   1   0   0   0   0                   0 
#30   0   1   0   1   1   1   1   0   0   0   0                   0 
#31   0   1   0   1   1   1   1   0   0   0   0                   0 
EFCR    LCK VMX^SGX [SENTER] [ SGX ] LMC                            
#0        -   -   -   -   -   -   -   -                             
#1        -   -   -   -   -   -   -   -                             
#2        -   -   -   -   -   -   -   -                             
#3        -   -   -   -   -   -   -   -                             
#4        -   -   -   -   -   -   -   -                             
#5        -   -   -   -   -   -   -   -                             
#6        -   -   -   -   -   -   -   -                             
#7        -   -   -   -   -   -   -   -                             
#8        -   -   -   -   -   -   -   -                             
#9        -   -   -   -   -   -   -   -                             
#10       -   -   -   -   -   -   -   -                             
#11       -   -   -   -   -   -   -   -                             
#12       -   -   -   -   -   -   -   -                             
#13       -   -   -   -   -   -   -   -                             
#14       -   -   -   -   -   -   -   -                             
#15       -   -   -   -   -   -   -   -                             
#16       -   -   -   -   -   -   -   -                             
#17       -   -   -   -   -   -   -   -                             
#18       -   -   -   -   -   -   -   -                             
#19       -   -   -   -   -   -   -   -                             
#20       -   -   -   -   -   -   -   -                             
#21       -   -   -   -   -   -   -   -                             
#22       -   -   -   -   -   -   -   -                             
#23       -   -   -   -   -   -   -   -                             
#24       -   -   -   -   -   -   -   -                             
#25       -   -   -   -   -   -   -   -                             
#26       -   -   -   -   -   -   -   -                             
#27       -   -   -   -   -   -   -   -                             
#28       -   -   -   -   -   -   -   -                             
#29       -   -   -   -   -   -   -   -                             
#30       -   -   -   -   -   -   -   -                             
#31       -   -   -   -   -   -   -   -                             
EFER     SCE LME LMA NX SVM LMS FFX TCE MCM WBI UAI IBRS            
#0        1   1   1   1   0   0   0   0   0   0   0   1             
#1        1   1   1   1   0   0   0   0   0   0   0   1             
#2        1   1   1   1   0   0   0   0   0   0   0   1             
#3        1   1   1   1   0   0   0   0   0   0   0   1             
#4        1   1   1   1   0   0   0   0   0   0   0   1             
#5        1   1   1   1   0   0   0   0   0   0   0   1             
#6        1   1   1   1   0   0   0   0   0   0   0   1             
#7        1   1   1   1   0   0   0   0   0   0   0   1             
#8        1   1   1   1   0   0   0   0   0   0   0   1             
#9        1   1   1   1   0   0   0   0   0   0   0   1             
#10       1   1   1   1   0   0   0   0   0   0   0   1             
#11       1   1   1   1   0   0   0   0   0   0   0   1             
#12       1   1   1   1   0   0   0   0   0   0   0   1             
#13       1   1   1   1   0   0   0   0   0   0   0   1             
#14       1   1   1   1   0   0   0   0   0   0   0   1             
#15       1   1   1   1   0   0   0   0   0   0   0   1             
#16       1   1   1   1   0   0   0   0   0   0   0   1             
#17       1   1   1   1   0   0   0   0   0   0   0   1             
#18       1   1   1   1   0   0   0   0   0   0   0   1             
#19       1   1   1   1   0   0   0   0   0   0   0   1             
#20       1   1   1   1   0   0   0   0   0   0   0   1             
#21       1   1   1   1   0   0   0   0   0   0   0   1             
#22       1   1   1   1   0   0   0   0   0   0   0   1             
#23       1   1   1   1   0   0   0   0   0   0   0   1             
#24       1   1   1   1   0   0   0   0   0   0   0   1             
#25       1   1   1   1   0   0   0   0   0   0   0   1             
#26       1   1   1   1   0   0   0   0   0   0   0   1             
#27       1   1   1   1   0   0   0   0   0   0   0   1             
#28       1   1   1   1   0   0   0   0   0   0   0   1             
#29       1   1   1   1   0   0   0   0   0   0   0   1             
#30       1   1   1   1   0   0   0   0   0   0   0   1             
#31       1   1   1   1   0   0   0   0   0   0   0   1             
XCR0     FPU SSE AVX MPX 512 MPK CEU CES AMX APX LWP                
#0        1   1   1   0   7   1   0   0   0   0   0                 
#1        1   1   1   0   7   1   0   0   0   0   0                 
#2        1   1   1   0   7   1   0   0   0   0   0                 
#3        1   1   1   0   7   1   0   0   0   0   0                 
#4        1   1   1   0   7   1   0   0   0   0   0                 
#5        1   1   1   0   7   1   0   0   0   0   0                 
#6        1   1   1   0   7   1   0   0   0   0   0                 
#7        1   1   1   0   7   1   0   0   0   0   0                 
#8        1   1   1   0   7   1   0   0   0   0   0                 
#9        1   1   1   0   7   1   0   0   0   0   0                 
#10       1   1   1   0   7   1   0   0   0   0   0                 
#11       1   1   1   0   7   1   0   0   0   0   0                 
#12       1   1   1   0   7   1   0   0   0   0   0                 
#13       1   1   1   0   7   1   0   0   0   0   0                 
#14       1   1   1   0   7   1   0   0   0   0   0                 
#15       1   1   1   0   7   1   0   0   0   0   0                 
#16       1   1   1   0   7   1   0   0   0   0   0                 
#17       1   1   1   0   7   1   0   0   0   0   0                 
#18       1   1   1   0   7   1   0   0   0   0   0                 
#19       1   1   1   0   7   1   0   0   0   0   0                 
#20       1   1   1   0   7   1   0   0   0   0   0                 
#21       1   1   1   0   7   1   0   0   0   0   0                 
#22       1   1   1   0   7   1   0   0   0   0   0                 
#23       1   1   1   0   7   1   0   0   0   0   0                 
#24       1   1   1   0   7   1   0   0   0   0   0                 
#25       1   1   1   0   7   1   0   0   0   0   0                 
#26       1   1   1   0   7   1   0   0   0   0   0                 
#27       1   1   1   0   7   1   0   0   0   0   0                 
#28       1   1   1   0   7   1   0   0   0   0   0                 
#29       1   1   1   0   7   1   0   0   0   0   0                 
#30       1   1   1   0   7   1   0   0   0   0   0                 
#31       1   1   1   0   7   1   0   0   0   0   0                 
CFG:     MFD MDM MVD TOM FWB MEM SNP PL  HMK                        
#0        1   0   1   1   1   0   0   0   0                         
#1        1   0   1   1   1   0   0   0   0                         
#2        1   0   1   1   1   0   0   0   0                         
#3        1   0   1   1   1   0   0   0   0                         
#4        1   0   1   1   1   0   0   0   0                         
#5        1   0   1   1   1   0   0   0   0                         
#6        1   0   1   1   1   0   0   0   0                         
#7        1   0   1   1   1   0   0   0   0                         
#8        1   0   1   1   1   0   0   0   0                         
#9        1   0   1   1   1   0   0   0   0                         
#10       1   0   1   1   1   0   0   0   0                         
#11       1   0   1   1   1   0   0   0   0                         
#12       1   0   1   1   1   0   0   0   0                         
#13       1   0   1   1   1   0   0   0   0                         
#14       1   0   1   1   1   0   0   0   0                         
#15       1   0   1   1   1   0   0   0   0                         
#16       1   0   1   1   1   0   0   0   0                         
#17       1   0   1   1   1   0   0   0   0                         
#18       1   0   1   1   1   0   0   0   0                         
#19       1   0   1   1   1   0   0   0   0                         
#20       1   0   1   1   1   0   0   0   0                         
#21       1   0   1   1   1   0   0   0   0                         
#22       1   0   1   1   1   0   0   0   0                         
#23       1   0   1   1   1   0   0   0   0                         
#24       1   0   1   1   1   0   0   0   0                         
#25       1   0   1   1   1   0   0   0   0                         
#26       1   0   1   1   1   0   0   0   0                         
#27       1   0   1   1   1   0   0   0   0                         
#28       1   0   1   1   1   0   0   0   0                         
#29       1   0   1   1   1   0   0   0   0                         
#30       1   0   1   1   1   0   0   0   0                         
#31       1   0   1   1   1   0   0   0   0                         
HWCR SMM SLW TLB WBI FF FERR IG  MW U-MW HLT SMI RSM SSE WRP MC  IO 
#0    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#1    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#2    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#3    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#4    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#5    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#6    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#7    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#8    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#9    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#10   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#11   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#12   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#13   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#14   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#15   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#16   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#17   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#18   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#19   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#20   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#21   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#22   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#23   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#24   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#25   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#26   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#27   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#28   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#29   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#30   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
#31   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0 
HWCR P0  PRB INC CPB HCF ROC SMU CSE IR SMMB TPR PG U-ID            
#0    0   0   1   0   0   1   0   0   1   1   1   0   0             
#1    0   0   1   0   0   1   0   0   1   1   1   0   0             
#2    0   0   1   0   0   1   0   0   1   1   1   0   0             
#3    0   0   1   0   0   1   0   0   1   1   1   0   0             
#4    0   0   1   0   0   1   0   0   1   1   1   0   0             
#5    0   0   1   0   0   1   0   0   1   1   1   0   0             
#6    0   0   1   0   0   1   0   0   1   1   1   0   0             
#7    0   0   1   0   0   1   0   0   1   1   1   0   0             
#8    0   0   1   0   0   1   0   0   1   1   1   0   0             
#9    0   0   1   0   0   1   0   0   1   1   1   0   0             
#10   0   0   1   0   0   1   0   0   1   1   1   0   0             
#11   0   0   1   0   0   1   0   0   1   1   1   0   0             
#12   0   0   1   0   0   1   0   0   1   1   1   0   0             
#13   0   0   1   0   0   1   0   0   1   1   1   0   0             
#14   0   0   1   0   0   1   0   0   1   1   1   0   0             
#15   0   0   1   0   0   1   0   0   1   1   1   0   0             
#16   0   0   1   0   0   1   0   0   1   1   1   0   0             
#17   0   0   1   0   0   1   0   0   1   1   1   0   0             
#18   0   0   1   0   0   1   0   0   1   1   1   0   0             
#19   0   0   1   0   0   1   0   0   1   1   1   0   0             
#20   0   0   1   0   0   1   0   0   1   1   1   0   0             
#21   0   0   1   0   0   1   0   0   1   1   1   0   0             
#22   0   0   1   0   0   1   0   0   1   1   1   0   0             
#23   0   0   1   0   0   1   0   0   1   1   1   0   0             
#24   0   0   1   0   0   1   0   0   1   1   1   0   0             
#25   0   0   1   0   0   1   0   0   1   1   1   0   0             
#26   0   0   1   0   0   1   0   0   1   1   1   0   0             
#27   0   0   1   0   0   1   0   0   1   1   1   0   0             
#28   0   0   1   0   0   1   0   0   1   1   1   0   0             
#29   0   0   1   0   0   1   0   0   1   1   1   0   0             
#30   0   0   1   0   0   1   0   0   1   1   1   0   0             
#31   0   0   1   0   0   1   0   0   1   1   1   0   0

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cyring commented Nov 27, 2024

CoreFreq v1.98.7

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