In this paper, a 65nm 1.2V 7-bit 1GSPS folding-interpolation A/D converter with a digitally self-calibrated vector generator is proposed. The folding rate is 2 and the interpolation rate is 8. A self-calibrated vector generation circuit with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage caused by process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm² and the power consumption is about 110mW with a 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at a 1GHz sampling frequency. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.