"High-Speed Interconnect Technology: On-Chip and Off-Chip."

Sachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani (2005)

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DOI: 10.1109/ICVD.2005.105

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Sachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani:
High-Speed Interconnect Technology: On-Chip and Off-Chip. VLSI Design 2005: 7

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