ulx3s

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Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board

camera verilog icestudio ov7670 ulx3s open-source-fpgas

Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board

camera verilog icestudio sobel ov7670 pipelined ulx3s sobel-edge-detector

SDR-HLS is a Master Thesis focused on the implementation and optimization of Software-defined radio using Amaranth High Level Synthesis.

software-defined ulx3s high-level-sy

Yet another faux-retro game system

fpga yosys cocotb prjtrellis ulx3s vexriscv

My samples and tests on the FGPA ULX3S board and opensource toolchain for ECP5

fpga verilog ulx3s

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