学习安全运营的记录 | The knowledge base of security operation
Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals
Online resources related to Detection Engineering. Detection rules, detection logic, attack samples, detection tests and emulation tools, logging configuration and best practices, event log references, resources, labs, data manipulation online tools, blogs, newsletters, good reads, books, trainings, podcasts, videos and twitter/x accounts.
Compile references of publications, devices, SoC and tools for technical watch. Provides CLI tool, web page, Ruby server and kind of PWA to search and get results from corpora.
Quickly pin sources, launch multiple investigations, and copy your references - All in 1-click!
SOC simulation system Uses Rsync file, Message Queue (Kafka...) mechanism to send to the Log receiving system. The Log receiving system includes Elastic Search and GrayLog for processing.
This repository is a group-project related to the class: IDG1293 - Avansert CSS
SideLine is a software-based power side-channel analysis vector. It uses delay-lines (located in SoC memory controllers) as power meters.
Repository for our 2022 SOC Healthy NYC data requests
Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and control hazards in a RISC processor, forwarding loops, branch mechanisms. Memory architectures in CPUs such as register files and caches. UART, I2C protocols.
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