Kernel/riscv64: Clean up the CSR interface a bit + drive-by stuff #25800
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The `[[gnu::packed]] alignas(u64)` where a no-op, and the SATP comparator is just the default one
* The CSR address is now mandated to be a compile time constant as a template argument, so we don't rely on inlining to make it a constant, which caused compilation failures in the past. * `CSR::[set|clear]_bits` now acts on enums which makes them a bit easier to use. * SSTATUS now provides a pre-shifted Bit enum instead of an Offset one making that safer/easier to use. * SIE reading/writing in now decoupled from the SCAUSE enum, removing some bit-fiddling in some places * Added the remaining SCAUSE/SIE values
It already takes a `FlatPtr` so no need to c-cast it to one...
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| template<Address address, Enum E> | ||
| requires(IsSame<UnderlyingType<E>, u64>) | ||
| ALWAYS_INLINE void set_bits(E bit_mask) | ||
| { | ||
| asm volatile("csrs %0, %1" ::"i"(address), "Kr"(bit_mask)); | ||
| } | ||
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| ALWAYS_INLINE void clear_bits(Address address, FlatPtr bit_mask) | ||
| template<Address address, Enum E> |
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Please keep the empty lines between the functions.
| ALWAYS_INLINE void set_bits(Address address, FlatPtr bit_mask) | ||
| template<Address address, Enum E> | ||
| requires(IsSame<UnderlyingType<E>, u64>) | ||
| ALWAYS_INLINE void set_bits(E bit_mask) |
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We might want to use these functions without enums in the future, but I guess we can add an overload for that then.
| // 10-12 Reserved | ||
| CounterOverflowInterrupt = SCAUSE_INTERRUPT_MASK | 13, | ||
| // 14-15 Reserved | ||
| // >= 16 Reserved |
| @@ -356,6 +383,8 @@ struct AK::Formatter<Kernel::RISCV64::CSR::SCAUSE> : AK::Formatter<FormatString> | |||
| return builder.put_string("Supervisor timer interrupt"sv); | |||
| case Kernel::RISCV64::CSR::SCAUSE::SupervisorExternalInterrupt: | |||
| return builder.put_string("Supervisor external interrupt"sv); | |||
| case Kernel::RISCV64::CSR::SCAUSE::CounterOverflowInterrupt: | |||
| return builder.put_string("Counter overflow interrupt"sv); | |||
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Please use the exact spelling from the RISC-V ISA manual, so "Counter-overflow interrupt".
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| ALWAYS_INLINE void set_bits(Address address, FlatPtr bit_mask) | ||
| template<Address address, Enum E> | ||
| requires(IsSame<UnderlyingType<E>, u64>) |
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We currently use FlatPtr as the CSR value type everywhere, not u64.
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| ALWAYS_INLINE void clear_bits(Address address, FlatPtr bit_mask) | ||
| template<Address address, Enum E> | ||
| requires(IsSame<UnderlyingType<E>, u64>) |
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Kernel: Add 2 missing includes
Kernel/riscv64: Simplify CSR struct decalarations a bit
The
[[gnu::packed]] alignas(u64)where a no-op, and the SATPcomparator is just the default one
Kernel/riscv64: Make the CSR helpers a bit safer/saner and add some more
template argument, so we don't rely on inlining to make it a constant,
which caused compilation failures in the past.
CSR::[set|clear]_bitsnow acts on enums which makes them a biteasier to use.
making that safer/easier to use.
some bit-fiddling in some places
Kernel: Remove redundant cast in
page_round_downIt already takes a
FlatPtrso no need to c-cast it to one...