High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform
R Nakamoto, S Sakuraba, A Martins… - IEICE transactions on …, 2011 - search.ieice.org
IEICE transactions on electronics, 2011•search.ieice.org
We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit
parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated
clock frequency of 20 GHz. Through some high frequency functional tests, we have
confirmed that the operation of the CLA has been successful. Through some low speed
tests, we have also confirmed that the operation of multiplication has been successful. In
addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit …
parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated
clock frequency of 20 GHz. Through some high frequency functional tests, we have
confirmed that the operation of the CLA has been successful. Through some low speed
tests, we have also confirmed that the operation of multiplication has been successful. In
addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit …
We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20 GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.
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