Abstract
The integration of a large number of transistors and device scaling results in the development of high-power density within Very Large-Scale Integrated (VLSI) circuits. Power density is directly proportional to chip temperature and grows exponentially as package density increases. As a result, considering temperature impacts at all levels of the VLSI design cycle becomes a fundamental phenomenon because it reduces a circuit’s performance and dependability. To decrease the power density of the circuit, a bi-partitioning heuristic approach based on Shannon’s expansion is provided in this study to offset the effect of temperature. Following bi-partitioning, the co-factored sub-circuits are transformed into cutting-edge AND-Inverter Graphs (AIGs) based on multi-level logic. The MCNC benchmark synthesis results indicate a maximum improvement of 36% area and 21.51% power density over the espresso tool-based decomposition.
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References
Sankaranarayanan K, Velusamy S, Stan M, Skadron K (2005) A case for thermal-aware floorplanning at the microarchitectural level. J Instr-Level Parallelism 7(1):1–16
Huang W, Sankaranarayanan K, Skadron K et al (2008) Accurate, pre-RTL temperature-aware design using a parameterized, geometric thermal model. IEEE Trans Comput 57(9):1277–1288
Shang L, Dick RP (2006) Thermal crisis: challenges and potential solutions. IEEE Potentials 25(5):31–35
Gunther, Binns SF, Carmean DM, Hall JC (2001) Managing the impact of increasing microprocessor power consumption. Intel Technol J 5(1):1–9
Pedram M, Nazarian S (2006) Thermal modeling, analysis, and management in VLSI circuits: principles and methods. Proc IEEE 94(8):1487–1501
Das A, Hareesh YC, Pradhan SN (2020) NSGA-II based thermal-aware mixed dual reed-muller network synthesis using parallel tabular technique. J Circ Syst Comput
Kandasamy N, Ahmad F, Telagam N (2018) Shannon logic based novel QCA full adder design with energy dissipation analysis. Int J Theor Phys 57(12):3702–3715
Das A, Pradhan SN (2019) Thermal-aware output polarity selection based on and-inverter graph manipulation. Recent Adv Electr Electron Eng 12(1):30–39
Lavagno L (1995) Timed Shannon circuits: a power-efficient design style and synthesis tool. In: 32nd Design automation conference. IEEE, pp 254–260
Das A, Choudhury SR, Kumar BK, Pradhan SN (2012) An elitist area-power density trade-off in VLSI floorplan using genetic algorithm. In: 7th International conference on electrical and computer engineering. IEEE, pp 729–732
Das A, Kumar Singh V, Nath Pradhan S (2022) Shared reduced ordered binary decision diagram-based thermal-aware network synthesis. Int J Circ Theory Appl 50(6):2271–2286
Sentovich EM, Singh KJ, Lavagno L, Moon C, Murgai R, Saldanha A, Savoj H, Stephan PR, Brayton RK, Sangiovanni-Vincentelli A (1992) SIS: a system for sequential circuit synthesis
Singh VK, Sarkar T, Pradhan SN (2021) Power-aware testing for maximum fault coverage in analog and digital circuits simultaneously. IETE Tech Rev 1–15
Brayton RK, Hachtel GD, McMullen C, Sangiovanni-Vincentelli A (1984) Logic minimization algorithms for VLSI synthesis, vol 2. Springer Science & Business Media
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Das, A., Singh, V.K., Pradhan, S.N. (2023). Temperature Aware Bi-partitioning Multi-level Logic Synthesis. In: Kumar, R., Verma, A.K., Sharma, T.K., Verma, O.P., Sharma, S. (eds) Soft Computing: Theories and Applications. Lecture Notes in Networks and Systems, vol 627. Springer, Singapore. https://doi.org/10.1007/978-981-19-9858-4_35
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DOI: https://doi.org/10.1007/978-981-19-9858-4_35
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