@@ -173,18 +173,20 @@ unsafe impl<T> Sync for AtomicPtr<T> {}
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/// Atomic memory orderings
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///
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- /// Memory orderings limit the ways that both the compiler and CPU may reorder
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- /// instructions around atomic operations. At its most restrictive,
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- /// "sequentially consistent" atomics allow neither reads nor writes
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- /// to be moved either before or after the atomic operation; on the other end
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- /// "relaxed" atomics allow all reorderings .
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+ /// Memory orderings specify the way atomic operations synchronize memory.
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+ /// In its weakest [`Relaxed`][Ordering::Relaxed], only the memory directly touched by the
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+ /// operation is synchronized. On the other hand, a store-load pair of [`SeqCst`][Ordering::SeqCst]
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+ /// operations synchronize other memory while additionally preserving a total order of such
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+ /// operations across all threads .
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///
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/// Rust's memory orderings are [the same as
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/// LLVM's](https://llvm.org/docs/LangRef.html#memory-model-for-concurrent-operations).
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///
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/// For more information see the [nomicon].
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///
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/// [nomicon]: ../../../nomicon/atomics.html
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+ /// [Ordering::Relaxed]: #variant.Relaxed
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+ /// [Ordering::SeqCst]: #variant.SeqCst
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#[ stable( feature = "rust1" , since = "1.0.0" ) ]
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#[ derive( Copy , Clone , Debug ) ]
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#[ non_exhaustive]
@@ -234,8 +236,8 @@ pub enum Ordering {
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/// For loads it uses [`Acquire`] ordering. For stores it uses the [`Release`] ordering.
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///
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/// Notice that in the case of `compare_and_swap`, it is possible that the operation ends up
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- /// not performing any store and hence it has just `Acquire` ordering. However,
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- /// `AcqRel` will never perform [`Relaxed`] accesses.
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+ /// not performing any store and hence it has just [ `Acquire`] ordering. However,
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+ /// [ `AcqRel`][`AcquireRelease`] will never perform [`Relaxed`] accesses.
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///
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/// This ordering is only applicable for operations that combine both loads and stores.
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///
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