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Commits on Aug 5, 2024

• [CORRECTIVE] Fix erroneous example library files.

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Commits on Nov 28, 2017

• Updated the example designs to utilize the design parameters propagation. Slightly adjusted the instruction decoder to work better.

  TermosPullo

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Commits on Aug 14, 2017

• Fixed invalid references.

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Commits on Jul 27, 2017

• Added more comments, renamed wb-to-cpu-bridge.

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Commits on Jul 26, 2017

• Added number of descriptions to IP-XACT metadata.

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Commits on May 18, 2017

• Revised the catalogs, so that new tutorials have corresponding catalogs and restructured large catalogs to be hierarchical.

  TermosPullo

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Commits on May 16, 2017

• Adjusted the designs to utilize data memory for local memory, rather than an internal register array.

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• Renamed mem_control to peripheral_control.

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Commits on May 15, 2017

• Removed the unneeded do file.

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• Reimplemented the test setups for the nomeclature and did the corrections required by this.

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Commits on May 10, 2017

• Revised the nomenclature of the IP-XACT metadata.

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Commits on Apr 26, 2017

• Consolidated program test benches to a test instruction memory.

  TermosPullo

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Commits on Apr 19, 2017

• Revised the naming of memory maps and address spaces, so that all elements use a single format.

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• Adjusted the memory example to work with the changes in the core. Moreover, added example test programs for peripherals.

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Commits on Apr 18, 2017

• Refactored the instruction decoder to support branching. This also means that the actual decoding is combinatorial, while most of the output is effective on the next clock cycle.

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Commits on Apr 13, 2017

• Now the instruction decoder uses program counter and instruction address instead of stall signal.

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• Now each peripheral has a proper implementation. Moreover, replaced data passer and riemann sum with SPI master and sum buffer.

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Commits on Apr 10, 2017

• Revised the register of core example.

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Commits on Apr 7, 2017

• Now the execution is stalled while memory controller is busy. Moreover, this is the first version with any kind of peripheral access.

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Commits on Apr 5, 2017

• Now the most important core functions work at least superficially.

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Commits on Apr 3, 2017

• Now the example core has an early implementation that compiles and stores literals to registers.

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Commits on Mar 31, 2017

• Implemented the wishbone CPU wrapper plus test.

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• Unified some of the nomenclature.

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Commits on Mar 30, 2017

• Renamed library of wishbone bus definition and template slave, so that those follow a more explicit convention.

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• Supplemented the memory maps and address spaces as well as their mappings to buses.

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Commits on Mar 29, 2017

• Adjusted the structure of the core so that it has separate units for clock and registers. Moreover, now also the data and clock are distributed along system bus rather than as a master output.

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Commits on Mar 27, 2017

• Added an early version external wishbone memory.

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• Early version of address space and memory map definitions.

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• Created an initial version of the memory example.

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Commits on Mar 24, 2017

• Adjusted the tests of wishbone b4.

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• Initial version of new wishbone cores

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Commits on Mar 6, 2017

• Now the SPI bus definition has descriptions.

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Commits on Mar 1, 2017

• Added files for the bus definition example. Also updated the catalogs.

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Commits on Feb 22, 2017

• Corrected spacing for SystemC implementation of the wishbone_bus.

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• Replaced tabs with four spaces in the code.

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