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Overhaul "Pixel FIFO" article into "Rendering Internals"
Also avoid describing SameBoy internals, instead relying on it when otherwise corroborated, or on schematics and/or test ROMs when possible. Restructure the article to describe behavior more than components, especially in a way that is more friendly to someone not knowing what all the components are about. Add a diagram, too, and move the mode timing diagram to the STAT article, where it belongs just as well, but where it will be more visible and thus more useful.
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Diff for: custom/style.css

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body {
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font-family: "Inter";
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/* Enable some font features for Inter (https://rsms.me/inter/#features/calt) */
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/* Enable some font features for Inter (https://rsms.me/inter/#features) */
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font-feature-settings: "ss01", /* Alternate (Open) digits */ "ss02",
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/* Disambiguation gliphs */ "case";
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/* Disambiguation glyphs */ "case", /* No contextual alternatives (e.g. 3x9 → 3×9) */ "calt" 0;
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/* Case alternates */
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letter-spacing: -0.005em;
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/* equals -0.5% */
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margin: 25px 0px 25px 0px;
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}
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/* Classes for custom table styling */
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table.compact th {
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padding: 3px 5px;
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}
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/* Global CSS variables */
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:root {

Diff for: src/Power_Up_Sequence.md

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The boot ROM is responsible for the automatic colorization of monochrome-only games when run on a GBC.
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When in DMG compatibility mode, the [CGB palettes](<#LCD Color Palettes (CGB only)>) are still being used: the background uses BG palette 0 (likely because the entire [attribute map](<#BG Map Attributes (CGB Mode only)>) is set to all zeros), and objects use OBJ palette 0 or 1 depending on bit 4 of [their attribute](<#Byte 3 — Attributes/Flags>).
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When in DMG compatibility mode, the [CGB palettes](<#LCD Color Palettes (CGB only)>) are still being used: the background uses BG palette 0 (likely because the entire [attribute map](<#BG Map attributes (CGB Mode only)>) is set to all zeros), and objects use OBJ palette 0 or 1 depending on bit 4 of [their attribute](<#Byte 3 — Attributes/Flags>).
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[`BGP`, `OBP0`, and `OBP1`](<#LCD Monochrome Palettes>) actually index into the CGB palettes instead of the DMG's shades of grey.
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The boot ROM picks a compatibility palette using an ID computed using the following algorithm:

Diff for: src/Rendering_Internals.md

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Diff for: src/STAT.md

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::: tip TERMINOLOGY
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A *dot* is the shortest period over which the PPU can output one pixel: is it equivalent to 1 T-state on DMG or on CGB single-speed mode or 2 T-states on CGB double-speed mode. On each dot during mode 3, either the PPU outputs a pixel or the fetcher is stalling the [FIFOs](<#Pixel FIFO>).
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A *dot* is the shortest period over which the PPU can output one pixel: is it equivalent to 1 T-state on DMG or on CGB single-speed mode or 2 T-states on CGB double-speed mode. On each dot during mode 3, either the PPU outputs a pixel or the fetcher is stalling the [FIFOs](<#Rendering Internals>).
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:::
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0 | Nothing (HBlank) | 85 to 208 dots (20 to 49 µs) depending on previous mode 3 duration | VRAM, OAM, CGB palettes
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1 | Nothing (VBlank) | 4560 dots (1087 µs, 10 scanlines) | VRAM, OAM, CGB palettes
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## Properties of STAT modes
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## STAT modes
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{{#include imgs/ppu_modes_timing.svg:2:}}
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Unlike most game consoles, the Game Boy can pause the dot clock briefly,
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making Mode 3 longer and Mode 0 shorter. It routinely takes a 6 to 11 dot
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break to fetch an OBJ's tile between background tile pattern fetches.
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break to fetch an OBJ's tile between background tile fetches.
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On DMG and GBC in DMG mode, mid-scanline writes to [`BGP`](<#FF47 — BGP (Non-CGB Mode only): BG palette data>)
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allow observing this behavior, as the delay from drawing an OBJ shifts the
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write's effect to the left by that many dots.

Diff for: src/SUMMARY.md

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- [LCD Status](./STAT.md)
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- [Scrolling](./Scrolling.md)
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- [Palettes](./Palettes.md)
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- [Pixel FIFO](./pixel_fifo.md)
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- [Rendering internals](./Rendering_Internals.md)
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- [Sound Controller](./Sound_Controller.md)
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- [Joypad Input](./Joypad_Input.md)
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- [Serial Data Transfer](./Serial_Data_Transfer_(Link_Cable).md)

Diff for: src/Scrolling.md

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### Scrolling
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The scroll registers are re-read on each [tile fetch](<#Get Tile>), except for the low 3 bits of SCX, which are only read at the beginning of the scanline (for the initial shifting of pixels).
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The scroll registers are re-read on each [tile fetch](<#Get tile ID>), except for the low 3 bits of SCX, which are only read at the beginning of the scanline (for the initial shifting of pixels).
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All models before the CGB-D read the Y coordinate once for each bitplane (so a very precisely timed SCY write allows "desyncing" them), but CGB-D and later use the same Y coordinate for both no matter what.
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Diff for: src/Tile_Maps.md

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the memory areas `$9800-$9BFF` and `$9C00-$9FFF`. Any of these maps can be used to
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display the Background or the Window.
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## Tile Indexes
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## Tile indices
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Each tile map contains the 1-byte indexes of the
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tiles to be displayed.
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Each tile map contains the 1-byte indices of the tiles to be displayed.
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Tiles are obtained from the Tile Data Table using either of the two
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addressing modes (described in [VRAM Tile Data](<#VRAM Tile Data>)), which
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Since one tile has 8x8 pixels, each map holds a 256x256 pixels picture.
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Only 160x144 of those pixels are displayed on the LCD at any given time.
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## BG Map Attributes (CGB Mode only)
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## BG Map attributes (CGB Mode only)
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In CGB Mode, an additional map of 32x32 bytes is stored in VRAM Bank 1
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(each byte defines attributes for the corresponding tile-number map

Diff for: src/imgs/ppu_overview.svg

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