esp32c3: corrupted log output when light sleep is enabled (IDFGH-7809) #9343
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Hi @HiFiPhile, could you please check if #7341 (comment) helps in this case? |
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I looked deeper this issue, it's a host side With my example, 4 groups of log are printed: First 3 groups are separated by 10-20ms, last group is cutted by half with 250ms interval. In uart level there is no corruption. So it means before entering light sleep there is no waiting for uart buffer flush. I won't say this behavior is buggy, but it's better to add an option to flush uart log buffer before sleep. What's interesting is the host side It's only This comment is suspicious: esp-idf/tools/idf_monitor_base/serial_handler.py Lines 109 to 112 in 9b8c558 |
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I have tried the attached project on Linux and it works perfectly well. It is possible that this is a Windows issue. |
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@HiFiPhile In my local environment (Host: Windows 10 + PuTTY, Board: ESP32-C3 DevKitM-1 v1.0, esp-idf commit 94cfe394), I did not reproduce the issue. Below is my test code: /*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: CC0-1.0
*/
#include "freertos/FreeRTOS.h"
#include "freertos/event_groups.h"
#include "esp_log.h"
#include "esp_pm.h"
static const char *TAG = "Issue/9343";
static void idfgh_7809(void)
{
int tLoop = 0;
while (1)
{
if(xTaskGetTickCount() - tLoop > pdMS_TO_TICKS(4000))
{
tLoop = xTaskGetTickCount();
ESP_LOGI(TAG, "In main task 1 %s", "dummy 1");
ESP_LOGI(TAG, "In main task 1 %s", "dummy 1");
vTaskDelay(pdMS_TO_TICKS(20));
ESP_LOGI(TAG, "In main task 1 %s", "dummy 1");
ESP_LOGI(TAG, "In main task 1 %s", "dummy 1");
vTaskDelay(pdMS_TO_TICKS(20));
ESP_LOGI(TAG, "In main task 1 %s", "dummy 1");
ESP_LOGI(TAG, "In main task 2 %s", "dummy 2");
vTaskDelay(pdMS_TO_TICKS(20));
ESP_LOGI(TAG, "In main task 3 %s", "dummy 3");
ESP_LOGI(TAG, "In main task 4 %s", "dummy 4");
}
else
{
vTaskDelay(pdMS_TO_TICKS(250));
}
}
}
void app_main(void)
{
#if CONFIG_PM_ENABLE
// Configure dynamic frequency scaling:
// maximum and minimum frequencies are set in sdkconfig,
// automatic light sleep is enabled if tickless idle support is enabled.
esp_pm_config_esp32c3_t pm_config = {
.max_freq_mhz = CONFIG_EXAMPLE_MAX_CPU_FREQ_MHZ,
.min_freq_mhz = CONFIG_EXAMPLE_MIN_CPU_FREQ_MHZ,
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
.light_sleep_enable = true
#endif
};
ESP_ERROR_CHECK( esp_pm_configure(&pm_config) );
#endif // CONFIG_PM_ENABLE
idfgh_7809();
} |
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@esp-lis Thank you for looking at it. I haven't worked on the project recently, we can close the issue for now, if I met it again I'll come back. |
@HiFiPhile You can use If the UART module is not powered down during sleep (the implicit retention of UART Tx FIFO data during sleep ensures it is not lost), then there is no need to forcefully flush and clear the FIFO. This avoids missing sleep due to FIFO flushing. At a UART baud rate of 115200, clearing a 128-byte Tx FIFO would take: |
espressif-bot
added
Status: Done
Environment
git describe --tagsto find it):v5.0-dev-3202-ga2d5041492xtensa-esp32-elf-gcc --versionto find it):gcc version 8.4.0 (crosstool-NG esp-2021r2-patch3)Problem Description
When light sleep is enabled, uart log output become corrupted. First part of log is repeated multiples times.
Expected Behavior
With attached example:
Actual Behavior
With attached example:
Steps to reproduce
Compile and run attached example.
Code to reproduce this issue
Log_corrupt.zip
Debug Logs
Other items if possible
buildfolder (note this may contain all the code details and symbols of your project.)elf.zip
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