Design_Overview.md

Design Overview

In this section we will discuss a design conceptually and later in this tutorial we will try to use the Vitis tools to implement the design on a Versal device. The arrow in the below diagram represents the control path:

flowchart LR
   A[APU] -.-> B[MM2S]
   A[APU] -.-> C[MM2S]
   B --> D[MatMul]
   C --> D[MatMul]
   D --> E[S2MM]
   E --> F[DDR]
   A -.-> F

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The plan is to send the data from APU/host application to AI Engine to perform Matrix Multiplication and save the output result in DDR, then use the APU to read the data from DDR and compare the results to print whether the test is a "Pass" or "Fail".

We will use the AMD provided platform instead of a custom platform to steer away from platform creation flow and to keep the tutorial as a beginner’s guide.

Here is the step-by-step guide to design a Versal design from scratch:

1. Prepare AI Engine kernel
2. Prepare HLS kernels
3. Create a host application using AMD VCK190 platform
4. Use Vitis Linker and Packager to build the design

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