-
Notifications
You must be signed in to change notification settings - Fork 15
/
Copy pathsupport.py
132 lines (116 loc) · 3.79 KB
/
support.py
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
"""Support examples."""
import argparse
import sys
from pyfpga.factory import Factory, TOOLS
parser = argparse.ArgumentParser()
parser.add_argument(
'--tool', default='openflow',
choices=list(TOOLS.keys())
)
args = parser.parse_args()
print(f'INFO: the Tool Under Test is {args.tool}')
print('INFO: checking basic Verilog Support')
prj = Factory(args.tool)
prj.add_vlog('../examples/sources/vlog/blink.v')
prj.set_top('Blink')
prj.make(last='syn')
print('INFO: checking advanced Verilog Support')
prj = Factory(args.tool)
prj.add_vlog('../examples/sources/vlog/*.v')
prj.set_top('Top')
prj.add_include('../examples/sources/vlog/include1')
prj.add_include('../examples/sources/vlog/include2')
prj.add_define('DEFINE1', '1')
prj.add_define('DEFINE2', '1')
prj.add_param('FREQ', '1')
prj.add_param('SECS', '1')
prj.make(last='syn')
try:
print('INFO: checking Verilog Includes Support')
prj = Factory(args.tool)
prj.add_vlog('../examples/sources/vlog/*.v')
prj.set_top('Top')
prj.add_define('DEFINE1', '1')
prj.add_define('DEFINE2', '1')
prj.add_param('FREQ', '1')
prj.add_param('SECS', '1')
prj.make(last='syn')
sys.exit('ERROR: something does not work as expected')
except SystemExit:
raise
except Exception:
pass
try:
print('INFO: checking Verilog Defines Support')
prj = Factory(args.tool)
prj.add_vlog('../examples/sources/vlog/*.v')
prj.set_top('Top')
prj.add_include('../examples/sources/vlog/include1')
prj.add_include('../examples/sources/vlog/include2')
prj.add_param('FREQ', '1')
prj.add_param('SECS', '1')
prj.make(last='syn')
sys.exit('ERROR: something does not work as expected')
except SystemExit:
raise
except Exception:
pass
try:
print('INFO: checking Verilog Parameters Support')
prj = Factory(args.tool)
prj.add_vlog('../examples/sources/vlog/*.v')
prj.set_top('Top')
prj.add_include('../examples/sources/vlog/include1')
prj.add_include('../examples/sources/vlog/include2')
prj.add_define('DEFINE1', '1')
prj.add_define('DEFINE2', '1')
prj.make(last='syn')
sys.exit('ERROR: something does not work as expected')
except SystemExit:
raise
except Exception:
pass
if args.tool not in ['ise']:
print('INFO: checking basic System Verilog Support')
prj = Factory(args.tool)
prj.add_slog('../examples/sources/slog/blink.sv')
prj.set_top('Blink')
prj.make(last='syn')
print('INFO: checking advanced System Verilog Support')
prj = Factory(args.tool)
prj.add_slog('../examples/sources/slog/*.sv')
prj.set_top('Top')
prj.add_include('../examples/sources/slog/include1')
prj.add_include('../examples/sources/slog/include2')
prj.add_define('DEFINE1', '1')
prj.add_define('DEFINE2', '1')
prj.add_param('FREQ', '1')
prj.add_param('SECS', '1')
prj.make(last='syn')
if args.tool not in ['openflow']:
print('* INFO: checking basic VHDL Support')
prj = Factory(args.tool)
prj.add_vhdl('../examples/sources/vhdl/blink.vhdl')
prj.set_top('Blink')
prj.make(last='syn')
print('* INFO: checking advanced VHDL Support')
prj = Factory(args.tool)
prj.add_vhdl('../examples/sources/vhdl/*.vhdl', 'blink_lib')
prj.add_vhdl('../examples/sources/vhdl/top.vhdl')
prj.set_top('Top')
prj.add_param('FREQ', '1')
prj.add_param('SECS', '1')
prj.make(last='syn')
try:
print('INFO: checking VHDL Generics')
prj = Factory(args.tool)
prj.add_vhdl('../examples/sources/vhdl/*.vhdl', 'blink_lib')
prj.add_vhdl('../examples/sources/vhdl/top.vhdl')
prj.set_top('Top')
prj.make(last='syn')
sys.exit('ERROR: something does not work as expected')
except SystemExit:
raise
except Exception:
pass
print(f'INFO: {args.tool} support works as expected')