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Synthesis of asynchronous control circuits with automatically generated relative timing assumptions | IEEE Conference Publication | IEEE Xplore

Synthesis of asynchronous control circuits with automatically generated relative timing assumptions


Abstract:

This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshak...Show More

Abstract:

This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ensure functionality. Relative timing assumptions in the form "event a occurs before event b" can be used to remove redundant handshakes and associated logic. This paper presents a method for automatic generation of relative timing assumptions from the untimed specification. These assumptions can be used for area and delay optimization of the circuit. A set of relative timing constraints sufficient for the correct operation of the circuit is back-annotated to the designer. Experimental results for control circuits of a prototype iA32 instruction length decoding and steering unit called RAPPID (Revolving Asynchronous Pentium(R)Processor Instruction Decoder) shows significant improvements in area and delay over speed-independent circuits.
Date of Conference: 07-11 November 1999
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-5832-5
Print ISSN: 1092-3152
Conference Location: San Jose, CA, USA

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