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Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

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Abstract

3-D Networks-on-Chip (NoC) emerge as a potent solution to address both the interconnection and design complexity problems facing future Multiprocessor System-on-Chips (MPSoCs). Effective run-time mapping on such 3-D NoC-based MPSoCs can be quite challenging, as the arrival order and task graphs of the target applications are typically not known a priori, which can be further complicated by stringent energy requirements for NoC systems. This paper thus presents an energy-aware run-time incremental mapping algorithm (ERIM) for 3-D NoC which can minimize the energy consumption due to the data communications among processor cores, while reducing the fragmentation effect on the incoming applications to be mapped, and simultaneously satisfying the thermal constraints imposed on each incoming application. Specifically, incoming applications are mapped to cuboid tile regions for lower energy consumption of communication and the minimal routing. Fragment tiles due to system fragmentation can be gleaned for better resource utilization. Extensive experiments have been conducted to evaluate the performance of the proposed algorithm ERIM, and the results are compared against the optimal mapping algorithm (branch-and-bound) and two heuristic algorithms (TB and TL). The experiments show that ERIM outperforms TB and TL methods with significant energy saving (more than 10%), much reduced average response time, and improved system utilization.

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Authors and Affiliations

  1. Intelligent Chips and Systems Research Centre, Guangzhou Institute of Advanced Technology, Chinese Academy of Sciences, Guangzhou, 511458, China

    Xiao-Hang Wang

  2. Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, 310027, China

    Xiao-Hang Wang & Peng Liu

  3. Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, Nevada, U.S.A.

    Mei Yang & Ying-Tao Jiang

  4. Faculty of Engineering, Kore University, Catania, Italy

    Maurizio Palesi

  5. Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York, U.S.A.

    Michael C Huang

Authors
  1. Xiao-Hang Wang
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  2. Peng Liu
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  3. Mei Yang
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  4. Maurizio Palesi
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  5. Ying-Tao Jiang
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  6. Michael C Huang
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Corresponding author

Correspondence to Peng Liu.

Additional information

This work is supported by the National Natural Science Foundation of China under Grant Nos. 60873112 and 61028004, the National Natural Science Foundation of USA under Grant No. CNS-1126688.

The preliminary version of the paper was published in the Proceedings of NPC 2011.

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Wang, XH., Liu, P., Yang, M. et al. Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip. J. Comput. Sci. Technol. 28, 54–71 (2013). https://doi.org/10.1007/s11390-013-1312-x

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  • DOI: https://doi.org/10.1007/s11390-013-1312-x

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