Skip to main content
Springer Nature Link
Log in

An Efficient Memory-Address Remapping Technique for High-Throughput QC-LDPC Decoder

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

This paper presents an efficient memory-address remapping technique for a high-throughput quasi-cyclic low-density parity check (QC-LDPC) decoder. In general, an LDPC decoder needs a large size of embedded memories for the temporal storage of the check node process (CNP) and variable node process (VNP) outputs. To increase the decoder throughput, overlapping the CNP and VNP operations is necessary; however, the parallel operations are mainly restricted by the embedded memory bandwidth. This work presents an efficient memory management approach in an LDPC decoder, where the memory-address conflicts and redundant memory-read operations are effectively reduced by using a proposed memory-address remapping technique. As a result, parallel variable node unit operations significantly increase, leading to higher throughput. When the proposed approach is applied to the various code rates of IEEE std. 802.16-2009, increases in decoding speed of up to 1.52X per iteration are achieved for overlapped message passing algorithm-based architecture, along with considerable reductions in the number of memory-read accesses. Using a 0.13-\(\upmu \)m CMOS process, a QC-LDPC decoder with multi-code rates is implemented, and the experimental results show that the proposed decoder achieves considerable throughput area ratio increase with energy savings compared to the conventional approaches.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

References

  1. B. Booth, IEEE 802.3 10GBase-T Study Group Meeting (2004) http://www.ieee802.org/3/minutes/nov03/1103_10GBT_closing

  2. Y. Chen, K.K. Parhi, Overlapped message passing for quasi-cyclic low-density parity check codes. IEEE Trans. Circuits Syst. I Reg. Papers 51(6), 1106–1113 (Jun. 2004)

  3. T. Cormen et al., in Introduction to Algorithms, 3rd edn. (MIT Press. Cambridge, MA, 2009), pp. 323–369

  4. A. Darabiha et al., in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), vol. 5, pp. 5194–5197, 2005

  5. R.G. Gallager, Low-density parity-check codes. IRE Trans. Inf. Theory 8(1), 21–28 (1962)

    Article  MathSciNet  MATH  Google Scholar 

  6. H. Ge, “Investigation of LDPC code in DVB-S2”, Linkopings universitet SE-581 83 (Linkoping, Sweden, 2012)

  7. J. Jin, C. Tsui, in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS, 2009), pp. 2233–2236

  8. S.J. Kerry et al., IEEE P802.11n/D1.0: Draft Amendment to STANDARD Information Technology Part 11, IEEE 802.11 document, 2006

  9. T.-C Kuo, A. Wilson, in Proceedings of IEEE Custom Integrated Circuits Conference, (2008), pp. 527–530

  10. X. Li et al. in International Symposium Integrated Circuits, (2007) pp. 508–511

  11. Z. Li, B.V.K.V. Kumar, in Proceedings of 38th Asilomar Conference Signals, Systems and Computers, vol. 2 (2004), pp. 1990–1994

  12. C. Liu et al., Design of a multimode QC-LDPC decoder based on shift-routing network. IEEE Trans. Circuits Syst. II Exp. Briefs 56(9), 734–738 (Sep. 2009)

  13. D.J.C. MacKay, Good error-correcting codes based on very sparse matrices. IEEE Trans. Inf. Theory 45(2), 399–431 (Mar. 1999)

  14. M. Mansour, A turbo-decoding message-passing algorithm for sparse parity-check matrix codes. IEEE Trans. Signal Process. 54(11), 4376–4392 (Nov. 2006)

  15. R.B. Marks et al., IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Broadband Wireless Access Systems, IEEE 802.16 document, (2009)

  16. X.Y. Shih et al., An 8.29 mm2 52 mW multi-mode LDPC decoder design for mobile WiMAX system in 0.13 um CMOS process. IEEE J. Solid-State Circuits 43(3), 672–683 (Mar. 2008)

  17. Synopsys Inc., Nanosim user guide, Version A-2008.03, (Mountain View, CA, 2008)

  18. Z. Wang, Z. Cui, Low-complexity high-speed decoder design for quasi-cyclic LDPC codes. IEEE Trans. Very Large Scale Integr. Syst. 15(1), 104–114 (2007)

    Article  Google Scholar 

  19. Z. Wang et al., VLSI design for low-density parity-check code decoding. IEEE Circuits Syst. Mag. 11(1), 52–69 (Feb. 2011)

  20. K. Xu, C. Choy, A five-stage pipeline, 204 cycles/MB, single-port SRAM-based deblocking filter for H.264/AVC. IEEE Trans. Circuits Syst. Video Technol., 18 (2008)

  21. E. Yeo et al., in Proceedings 45th Midwest Symposium Circuits and Systems (MWCAS), vol. 3, (2002) pp. III-437-III-440

  22. T. Zhang, K.K. Parhi, in IEEE Workshop on Signal Processing Systems (SIPS’02), (2002) pp. 127–132

Download references

Acknowledgments

This work was supported by the IC Design Education Center (IDEC). This work was supported by a Grant from the National Research Foundation of Korea (NRF), funded by the Korea government (MEST) (No. 2012R1A2A2A01012471)

Author information

Authors and Affiliations

  1. The School of Electrical Engineering, Korea University, Seoul,  136-701, Korea

    Ji-Hwan Yoon & Jongsun Park

Authors
  1. Ji-Hwan Yoon
    View author publications

    You can also search for this author inPubMed Google Scholar

  2. Jongsun Park
    View author publications

    You can also search for this author inPubMed Google Scholar

Corresponding author

Correspondence to Jongsun Park.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Yoon, JH., Park, J. An Efficient Memory-Address Remapping Technique for High-Throughput QC-LDPC Decoder. Circuits Syst Signal Process 33, 3457–3473 (2014). https://doi.org/10.1007/s00034-014-9808-3

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-014-9808-3

Keywords