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A New Transmission Gate Cascode Current Mirror Charge Pump for Fast Locking Low Noise PLL

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Abstract

Charge Pump in a phase locked loop (PLL) generates non-ideal effects such as current mismatches at the output node and switching errors at the pull up and pull down networks. This work presents a novel transmission gate cascode current mirror charge pump circuit. The switches incorporated in this work are Transmission Gates which help to reduce various switching errors, and only one supply independent reference current source is used to have a minimum current mismatch. The performance analysis carried out in the Cadence design environment, and it is observed that the loop locks in 25 ns which is 50 % faster than the conventional charge pump. The control voltage absolutely has no ripple in it after locking which reduces the reference spur further. It could be achieved because the current mismatch is only about 7 %. This PLL operates at 2.5 GHz having a wide lock range of 0.5–2.8 GHz where average power consumption is 1.74 mW. Due to the use of cascade current mirror circuits, the output voltage swing that can be obtained is 1.79 V.

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Authors and Affiliations

  1. Department of Electronics and communication Engineering, National Institute of Technology, Rourkela, 769008, India

    Umakanta Nanda, Debiprasad Priyabrata Acharya & Sarat Kumar Patra

Authors
  1. Umakanta Nanda
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  2. Debiprasad Priyabrata Acharya
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  3. Sarat Kumar Patra
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Correspondence to Umakanta Nanda.

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Nanda, U., Acharya, D.P. & Patra, S.K. A New Transmission Gate Cascode Current Mirror Charge Pump for Fast Locking Low Noise PLL. Circuits Syst Signal Process 33, 2709–2718 (2014). https://doi.org/10.1007/s00034-014-9785-6

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  • DOI: https://doi.org/10.1007/s00034-014-9785-6

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