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On mapping cube graphs onto VLSI arrays

  • Session 5 VLSI
  • Conference paper
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Foundations of Software Technology and Theoretical Computer Science (FSTTCS 1984)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 181))

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Abstract

Formal models of linear, mesh and hexagonal arrays are presented. These arrays are well-suited for VLSI (very large scale integration). A model of a logical linear array, wherein adjacent processors may be separated by wires of arbitrary length, is also presented. Logical linear arrays are important computational structures suitable for implementation on a a wafer where fabrication errors may cause processors to be separated by arbitrarily long distances.

Cube graphs which are data-flow descriptions of some matrix and related computations are introduced. A mathematical technique is developed to construct algorithms for these array models from cube graphs. The technique is illustrated by constructing some published algorithms as well as some new algorithms.

This material is based on work supported by the National Science Foundation under grant number ECS-84-04399.

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Author information

Authors and Affiliations

  1. Department of Computer Science, University of Maryland, 20742, College Park, MD

    I. V. Ramakrishnan

  2. Department of Electrical Engineering, Rice University, 77001, Houston, TX

    P. J. Varman

Authors
  1. I. V. Ramakrishnan
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  2. P. J. Varman
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Mathai Joseph Rudrapatna Shyamasundar

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© 1984 Springer-Verlag Berlin Heidelberg

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Ramakrishnan, I.V., Varman, P.J. (1984). On mapping cube graphs onto VLSI arrays. In: Joseph, M., Shyamasundar, R. (eds) Foundations of Software Technology and Theoretical Computer Science. FSTTCS 1984. Lecture Notes in Computer Science, vol 181. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-13883-8_79

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  • DOI: https://doi.org/10.1007/3-540-13883-8_79

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-13883-9

  • Online ISBN: 978-3-540-39087-9

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