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ORCIDMing Ling
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
2020 – today
- 2025
[j32]Hucheng Li, Jianjun Chen, Ming Ling, Zizhen Chen, Yanping Lan, Qinyi Huang, Xinhong Li, Haotian You, Feng Wang, Xiaowen Han, Guoqing Zhou:
A framework for dynamic assessment of soil erosion and detection of driving factors in alpine grassland ecosystems using the RUSLE-InVEST (SDR) model and Geodetector: A case study of the source region of the Yellow River. Ecol. Informatics 85: 102928 (2025)- 2024
- [j31]Chao Wang
, Yali Yang, Hao Chen, Sha Xu, Yongfang Li, Ruoping Zhang, Ming Ling:
Fatigue life prediction driven by mesoscopic defect data. Eng. Appl. Artif. Intell. 131: 107773 (2024) - [j30]Zizhen Chen, Jianjun Chen, Yuemin Yue, Yanping Lan, Ming Ling, Xinhong Li, Haotian You, Xiaowen Han, Guoqing Zhou:
Tradeoffs among multi-source remote sensing images, spatial resolution, and accuracy for the classification of wetland plant species and surface objects based on the MRS_DeepLabV3+ model. Ecol. Informatics 81: 102594 (2024) - [j29]Xinhong Li, Jianjun Chen, Zizhen Chen, Yanping Lan, Ming Ling, Qinyi Huang, Hucheng Li, Xiaowen Han, Shuhua Yi:
Explainable machine learning-based fractional vegetation cover inversion and performance optimization - A case study of an alpine grassland on the Qinghai-Tibet Plateau. Ecol. Informatics 82: 102768 (2024) - [j28]Ming Ling, Zihao Feng, Zizhen Chen, Yanping Lan, Xinhong Li, Haotian You, Xiaowen Han, Jianjun Chen:
Evaluation of driving effects of carbon storage change in the source of the Yellow River: A perspective with CMIP6 future development scenarios. Ecol. Informatics 83: 102790 (2024) - [j27]Shan Shen, Hao Xu, Yongliang Zhou, Ming Ling, Wenjian Yu:
Ultra8T: A sub-threshold 8T SRAM with leakage detection. Integr. 98: 102233 (2024) - [j26]Qi Liu, Ming Ling, Yanxiang Zhu, Yibo Rui, Rui Wang:
Preventing short violations in clock routing with an SVM classifier before powerplanning and placement. Microelectron. J. 153: 106429 (2024) - [j25]Wenzhen Zhang, Ming Ling:
An improved point cloud denoising method in adverse weather conditions based on PP-LiteSeg network. PeerJ Comput. Sci. 10: e1832 (2024) - [j24]Ming Ling, Zhihao Feng, Ruiqi Chen, Yi Shao, Shidi Tang, Yanxiang Zhu:
Vina-FPGA-Cluster: Multi-FPGA Based Molecular Docking Tool With High-Accuracy and Multi-Level Parallelism. IEEE Trans. Biomed. Circuits Syst. 18(6): 1321-1337 (2024) - [c17]Shidi Tang, Xingxing Zhou, Ming Ling:
Modeling Equivariant Neural Networks for Hardware Acceleration, a Case Study on the Molecular Docking Tool DiffDock. PACRIM 2024: 1-6 - [c16]Zheng Lei, Renjie Hu, Fenghua Wang, Wei Wang, Xuejiao Tang, Ming Ling:
Project-Based Analog Circuit Experiment Design for Lane Detection and Tracking in Electric Trolley Systems. TALE 2024: 1-6 - [i7]Fang Jiang, Fei Tong, Hongyu Wang, Xiaoyu Cheng, Zhe Zhou, Ming Ling, Yuxing Mao:
PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching. CoRR abs/2405.03217 (2024) - 2023
- [j23]Ji Ding, Shidi Tang, Zheming Mei, Lingyue Wang, Qinqin Huang, Haifeng Hu, Ming Ling, Jiansheng Wu:
Vina-GPU 2.0: Further Accelerating AutoDock Vina and Its Derivatives with Graphics Processing Units. J. Chem. Inf. Model. 63(7): 1982-1998 (2023) - [j22]Shan Shen, Peng Cao, Ming Ling, Longxing Shi:
A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1223-1234 (2023) - [j21]Xingxing Zhou, Ming Ling, Qingde Lin, Shidi Tang, Jiansheng Wu, Haifeng Hu:
Effectiveness Analysis of Multiple Initial States Simulated Annealing Algorithm, a Case Study on the Molecular Docking Tool AutoDock Vina. IEEE ACM Trans. Comput. Biol. Bioinform. 20(6): 3830-3841 (2023) - [j20]Ming Ling, Qingde Lin, Ruiqi Chen, Haimeng Qi, Mengru Lin, Yanxiang Zhu, Jiansheng Wu:
Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 484-497 (2023) - [c15]Leilei Jin, Jiajie Xu, Wenjie Fu, Hao Yan, Xiao Shi, Ming Ling, Longxing Shi:
A Novel Delay Calibration Method Considering Interaction between Cells and Wires. DATE 2023: 1-6 - [c14]Fan Yang, Zheng Qing, Ming Ling, Wa An:
A New Process Framework for Managing the Fuzzy Front End of New Healthcare Device Development. HCI (24) 2023: 480-491 - [i6]Peng Tu, Xu Xie, Ming Ling, Min Yang, Guo Ai, Yawen Huang, Yefeng Zheng:
FemtoDet: An Object Detection Baseline for Energy Versus Performance Tradeoffs. CoRR abs/2301.06719 (2023) - [i5]Shan Shen, Hao Xu, Yongliang Zhou, Ming Ling, Wenjian Yu:
Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection. CoRR abs/2306.08936 (2023) - 2022
- [j19]Ming Ling, Hongxi Li, Xiang Yu:
A Quantitative Analysis and Optimization on the Cache Behavior Influenced by Literal Pools. IEEE Embed. Syst. Lett. 14(2): 95-98 (2022) - [j18]Leilei Jin, Wenjie Fu, Ming Ling, Longxing Shi:
A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming. IEEE Trans. Very Large Scale Integr. Syst. 30(4): 353-364 (2022) - [i4]Shan Shen, Peng Cao, Ming Ling, Longxing Shi:
A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model. CoRR abs/2202.11941 (2022) - 2021
- [j17]Ming Ling, Xiaoqian Lu, Guangmin Wang, Jiancong Ge:
Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence. IEEE Access 9: 17728-17743 (2021) - [j16]Yang Xiao, Ming Ling, Zhenming Liang, Jian Ding, Shi Zhan, Hai Hu, Bin Chen:
Dual fluoroscopic imaging and CT-based finite element modelling to estimate forces and stresses of grafts in anatomical single-bundle ACL reconstruction with different femoral tunnels. Int. J. Comput. Assist. Radiol. Surg. 16(3): 495-504 (2021) - [j15]Ming Ling, Qingde Lin, Ke Tan, Tianxiang Shao, Shan Shen, Jun Yang:
A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2197-2209 (2021) - 2020
- [j14]Junkai Xu, Fangyuan Cao, Shi Zhan, Ming Ling, Hai Hu, Peter B. Shull:
Mapping-Based Dosage of Gait Modification Selection for Multi-Parameter, Subject-Specific Gait Retraining. IEEE Access 8: 106354-106363 (2020) - [j13]Wenjie Fu, Leilei Jin, Ming Ling, Yu Zheng, Longxing Shi:
VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay Models. IEEE Access 8: 197194-197202 (2020) - [j12]Wenjie Fu, Ming Ling, Wei Wang, Longxing Shi:
AMPS: Accelerating McPAT Power Evaluation Without Cycle-Accurate Simulations. IEEE Embed. Syst. Lett. 12(1): 13-16 (2020) - [j11]Ming Ling, Jiancong Ge, Guangmin Wang:
Fast modeling L2 cache reuse distance histograms using combined locality information from software traces. J. Syst. Archit. 108: 101745 (2020) - [j10]Shan Shen, Tianxiang Shao, Xiaojing Shang, Yichen Guo, Ming Ling, Jun Yang, Longxing Shi:
TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 252-262 (2020) - [c13]Wenjie Fu, Leilei Jin, Ming Ling, Yu Zheng, Longxing Shi:
A Cross-Layer Power and Timing Evaluation Method for Wide Voltage Scaling. DAC 2020: 1-6 - [c12]Shan Shen, Liang Pang, Tianxiang Shao, Ming Ling, Xiao Shi, Longxing Shi:
TYMER: A Yield-based Performance Model for Timing-speculation SRAM. DAC 2020: 1-6 - [c11]Shan Shen, Tianxiang Shao, Ming Ling, Jun Yang, Longxing Shi:
Modeling and Designing of a PVT Auto-tracking Timing-speculative SRAM. DATE 2020: 1073-1078 - [i3]Ming Ling, Guangmin Wang, Jiancong Ge, Xiaoqian Lu:
Analytical Modeling the Multi-Core Shared Cache Behavior with Considerations of Data-Sharing and Coherence. CoRR abs/2007.11195 (2020)
2010 – 2019
- 2019
- [j9]Ming Ling, Xiaojing Shang, Shan Shen, Tianxiang Shao, Jun Yang:
Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM. IEEE Access 7: 111649-111661 (2019) - [j8]Ming Ling, Xiaojing Shang, Kecheng Ji, Longxing Shi:
Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations. Microprocess. Microsystems 64: 159-169 (2019) - [j7]Li Yang, Zhi Qi, Zeheng Liu, Hao Liu, Ming Ling, Longxing Shi, Xinning Liu:
An embedded implementation of CNN-based hand detection and orientation estimation algorithm. Mach. Vis. Appl. 30(6): 1071-1082 (2019) - [j6]Kaiyang Liu, Jun Peng, Liang He, Jianping Pan, Shuo Li, Ming Ling, Zhiwu Huang:
An Active Mobile Charging and Data Collection Scheme for Clustered Sensor Networks. IEEE Trans. Veh. Technol. 68(5): 5100-5113 (2019) - [c10]Wenjie Fu, Yu Zheng, Leilei Jin, Ming Ling:
A Fast Reduction Method for Path Process Variations Without Time-Consuming Training. ASICON 2019: 1-4 - [c9]Guangmin Wang, Jiancong Ge, Yunhao Yan, Ming Ling:
A Data-Sharing Aware and Scalable Cache Miss Rates Model for Multi-Core Processors with Multi-Level Cache Hierarchies. ICPADS 2019: 267-274 - [c8]Jiancong Ge, Ming Ling:
Fast Modeling of the L2 Cache Reuse Distance Histograms from Software Traces. ISPASS 2019: 145-146 - [c7]Xiaojing Shang, Ming Ling, Shan Shen, Tianxiang Shao, Jun Yang:
RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism. MEMSYS 2019: 451-458 - [c6]Ming Ling, Xin Xu, Yushen Gu, Zhihua Pan:
Does the ISA Really Matter? A Simulation Based Investigation. PACRIM 2019: 1-6 - [c5]Yunhao Yan, Ming Ling:
Accelerating the Analytical Modeling of Memory Level Parallelism by the Probability Analysis. PACRIM 2019: 1-6 - [i2]Shan Shen, Tianxiang Shao, Xiaojing Shang, Yichen Guo, Ming Ling, Jun Yang, Longxing Shi:
TS Cache: A Fast Cache with Timing-speculation Mechanism Under Low Supply Voltages. CoRR abs/1904.11200 (2019) - [i1]Ming Ling, Jiancong Ge, Guangmin Wang:
Fast Modeling L2 Cache Reuse Distance Histograms Using Combined Locality Information from Software Traces. CoRR abs/1907.05068 (2019) - 2018
- [j5]Shan Shen, Ming Ling, Yongtao Zhang, Longxing Shi:
Detecting the phase behavior on cache performance using the reuse distance vectors. J. Syst. Archit. 90: 85-93 (2018) - [j4]Kecheng Ji, Ming Ling, Longxing Shi, Jianping Pan:
An Analytical Cache Performance Evaluation Framework for Embedded Out-of-Order Processors Using Software Characteristics. ACM Trans. Embed. Comput. Syst. 17(4): 79:1-79:25 (2018) - 2017
- [j3]Kecheng Ji, Ming Ling, Yang Zhang, Longxing Shi:
An artificial neural network model of LRU-cache misses on out-of-order embedded processors. Microprocess. Microsystems 50: 66-79 (2017) - [j2]Kecheng Ji, Ming Ling, Longxing Shi:
Using the first-level cache stack distance histograms to predict multi-level LRU cache misses. Microprocess. Microsystems 55: 55-69 (2017) - [c4]Kecheng Ji, Ming Ling, Qin Wang, Longxing Shi, Jianping Pan:
AFEC: An analytical framework for evaluating cache performance in out-of-order processors. DATE 2017: 55-60 - [c3]Fengying Sun, Kecheng Ji, Ming Ling, Longxing Shi:
A trace-driven analytical model with less profiling overhead for DRAM access latencies. PACRIM 2017: 1-6 - [c2]Qin Wang, Kecheng Ji, Ming Ling, Longxing Shi:
A mechanistic model of memory level parallelism fed with cache miss rates. PACRIM 2017: 1-6 - 2013
- [c1]Jianping Wu, Ming Ling, Yang Zhang, Chen Mei, Huan Wang:
A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase Graph. ASICON 2013: 1-5 - 2012
- [j1]Jianping Wu, Ming Ling, Yang Zhang, Chen Mei, Huan Wang:
Dynamic Allocation of SPM Based on Time-Slotted Cache Conflict Graph for System Optimization. IEICE Trans. Inf. Syst. 95-D(8): 2039-2052 (2012)
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